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公开(公告)号：EP0513451B1
公开(公告)日：1997-07-23
申请号：EP91304420.2
申请日：1991-05-16
CPC分类号： G09G5/395 , G11C7/1075
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公开(公告)号：EP0429728B1
公开(公告)日：1994-06-15
申请号：EP89312532.8
申请日：1989-11-30
IPC分类号： G01R31/318 , G11C19/00
CPC分类号： G01R31/318558 , G01R31/318552 , G06F1/10 , G11C19/00
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3.发明授权
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公开(公告)号：EP0301253A2
公开(公告)日：1989-02-01
申请号：EP88110299.0
申请日：1988-06-28
摘要： The present invention concerns a line generator and a method for determining the individual pixels to be plotted for a line to be drawn in a display system. Coded representations of a plurality of lines are stored in a line definition table (12, in 42), the coded representation of each individual line comprising a string of data items representing the transitions between adjacent pixels to be plotted for drawing said individual line. Preferably, only coded representations of lines up to a predetermined size (ie. the length of the line in the case of a straight line) are stored in the line definition table (12, in 42) and strings of data items for representing the pixels to be plotted for longer lines to be drawn are still calculated (in 40) as in the prior art. In this case, means (28,46) are provided for determining whether there are coded representations of a line to be drawn in the line definition table, or not, and for passing control to the appropriate logic for determining the pixels to be plotted. In a preferred embodiment, the string of data items forming the coded representation of a line to be drawn is a string of binary digits and the value each bit in the string represents a transition in one of two directions. This provides a very compact representation of the line.
摘要翻译： 本发明涉及一种线生成器和一种用于确定要在显示系统中绘制的线绘制的各个像素的方法。 多行的编码表示被存储在行定义表（42中，42）中，每个单独行的编码表示包括表示要绘制所述各行的相邻像素之间的转换的数据项串。 优选地，只有直到预定尺寸（即，在直线的情况下的线的长度）的线的编码表示被存储在线定义表（12中，在42中）和用于表示像素的数据项的串 对于要绘制的较长线条，绘制的图仍然按现有技术计算（40）。 在这种情况下，提供用于确定是否存在要在线定义表中绘制的线的编码表示的装置（28,46），并且用于将控制传递到用于确定要绘制的像素的适当逻辑。 在优选实施例中，形成要绘制的线的编码表示的数据项串是二进制数字串，并且字符串中的每个位的值表示两个方向之一的转换。 这提供了线的非常紧凑的表示。
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公开(公告)号：EP0903922A2
公开(公告)日：1999-03-24
申请号：EP98307211.7
申请日：1998-09-07
发明人： Bowater, Ronald John , Butler, Nicholas David , Clarke, David Andrew , Renshaw, David Seager , Tuttle, Graham Hugh
IPC分类号： H04M3/50
CPC分类号： H04M3/493
摘要： A voice processing system 30 is connected to a switch 20 via multiple telephone lines 25, and provides a set of line objects 335, each line object being associated with one of the physical telephone lines. The line object allows a demarcation to be made between the underlying voice processing system software 335, and external business applications 310. Thus a line object supports a set of methods such as Get DTMF Tone, Play Audio, Answer call, and End call, to allow the external business applications 310 to perform desired operations on a telephone line. These methods are invoked via a set of corresponding IVR action objects 320, which in turn are integrated into the business application. The business application itself, and its IVR actions, regard the line objects effectively as servers to provide IVR functionality. The business application may therefore run partially or completely on a separate physical machine from the IVR system itself.
摘要翻译： 语音处理系统30通过多条电话线25连接到交换机20，并且提供一组线对象335，每条线对象与物理电话线之一相关联。 线对象允许在底层语音处理系统软件335和外部业务应用310之间进行分界。因此，线对象支持一组方法，例如获取DTMF音，播放音频，应答呼叫和结束呼叫，以 允许外部业务应用310在电话线上执行期望的操作。 这些方法通过一组相应的IVR动作对象320来调用，该对象又被集成到业务应用中。 业务应用程序本身及其IVR操作将线对象有效地视为服务器来提供IVR功能。 因此，业务应用程序可以部分或完全地在与IVR系统本身的单独物理机器上运行。
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公开(公告)号：EP0301253B1
公开(公告)日：1992-12-23
申请号：EP88110299.0
申请日：1988-06-28
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公开(公告)号：EP0429728A1
公开(公告)日：1991-06-05
申请号：EP89312532.8
申请日：1989-11-30
IPC分类号： G01R31/318 , G11C19/00
CPC分类号： G01R31/318558 , G01R31/318552 , G06F1/10 , G11C19/00
摘要： A logic circuit is presented comprising a plurality of registers 30, 39; each register 30 having first register latches 31, 41 for clocking data into the register 30 in response to a first clock signal 37 and second register latches for clocking data out of the register in response to a second clock signal 38, and combinatorial logic comprising address logic 4 for addressing data to a register and first suppression logic 33 for inhibiting the first clock signal input to the register in responsive to the address logic, wherein the logic circuit further comprises second suppression logic 34, 35 for inhibiting the second clock signal input to the register in collective response to the address logic and the first clock signal.
摘要翻译： 呈现包括多个寄存器30,39的逻辑电路; 每个寄存器30具有第一寄存器锁存器31,41，用于响应于第一时钟信号37将数据计时到寄存器30中;以及第二寄存器锁存器，用于响应于第二时钟信号38将数据输出寄存器;以及组合逻辑，包括地址 用于将数据寻址到寄存器的逻辑4和用于响应于地址逻辑禁止输入到寄存器的第一时钟信号的第一抑制逻辑33，其中逻辑电路还包括第二抑制逻辑34,35，用于禁止第二时钟信号输入 该寄存器集中响应地址逻辑和第一个时钟信号。
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公开(公告)号：EP0386870A3
公开(公告)日：1992-12-30
申请号：EP90300505.6
申请日：1990-01-18
发明人： West, Roderick Michael , Butler, Nicholas David , Sidoli, Paoli Gerardo , Larky, Steven Philip , Buttimer, Malcolm Douglas , Homewood Brian Clive
IPC分类号： G06F9/46
摘要： In a logic circuit having a plurality of clocked state latches (SRL) and combinatorial logic for functional processing of a task in response to functional clocking C′-B′ of the state latches, the state latches are additionally interconnected to form a scannable chain of latches, and task switching logic 12,14 is provided for suspending task processing by interrupting the functional clocking C′-B′ of the state latches and, during said suspension, for scanning the state latches such that existing contents of the state latches defining a task state can be saved from the state latches and/or new contents defining a task state can be loaded into the state latches. The invention provides an efficient means for switching tasks being performd by a logic circuit in a multiprocessing environment.
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公开(公告)号：EP0386870A2
公开(公告)日：1990-09-12
申请号：EP90300505.6
申请日：1990-01-18
发明人： West, Roderick Michael , Butler, Nicholas David , Sidoli, Paoli Gerardo , Larky, Steven Philip , Buttimer, Malcolm Douglas , Homewood Brian Clive
IPC分类号： G06F9/46
摘要： In a logic circuit having a plurality of clocked state latches (SRL) and combinatorial logic for functional processing of a task in response to functional clocking C′-B′ of the state latches, the state latches are additionally interconnected to form a scannable chain of latches, and task switching logic 12,14 is provided for suspending task processing by interrupting the functional clocking C′-B′ of the state latches and, during said suspension, for scanning the state latches such that existing contents of the state latches defining a task state can be saved from the state latches and/or new contents defining a task state can be loaded into the state latches. The invention provides an efficient means for switching tasks being performd by a logic circuit in a multiprocessing environment.
摘要翻译： 在具有多个时钟状态锁存器（SRL）的逻辑电路和用于响应于状态锁存器的功能时钟C min-B min的功能处理任务的组合逻辑，状态锁存器被附加地互连以形成可扫描链 锁存器和任务切换逻辑12,14用于通过中断状态锁存器的功能时钟C min -B min来中止任务处理，并且在所述暂停期间，用于扫描状态锁存器，使得状态锁存器的现有内容定义为 任务状态可以从状态锁存器和/或定义任务状态的新内容保存到状态锁存器中。 本发明提供了一种用于在多处理环境中切换由逻辑电路执行的任务的有效手段。
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