公开(公告)号：EP0505780A2

公开(公告)日：1992-09-30

申请号：EP92103747.9

申请日：1992-03-05

申请人： International Business Machines Corporation

发明人： Olnowich, Howard Thomas ,  Barker, Thomas Norman ,  Kogge, Peter Michael ,  Vandling III, Gilbert Clyde

IPC分类号： G06F15/16 ,  H04L12/56

CPC分类号： H04L1/0057 ,  G06F11/261 ,  G06F13/4022 ,  G06F15/17375 ,  G06F15/17393 ,  H04L7/0338 ,  H04L12/1881 ,  H04L49/15 ,  H04L49/1523 ,  H04L49/201 ,  H04L49/205 ,  H04Q11/0066 ,  H04Q11/0478

摘要： Disclosed is a dual priority switching apparatus for making input port to output port connections on a requested basis quickly and dynamically, in a standard mode from any one of the input ports to any one of the output ports, in a multi-cast mode from any one of the input ports to a fixed number of subsets of multiple output ports simultaneously, or in a broadcast mode from any one of the input ports to all output ports simultaneously, using a new high priority approach to resolve either broadcast or multi-cast contention amongst input ports. The disclosed priority broadcast and multi-cast functions provide a more complex, yet faster and higher powered broadcast and multi-cast function. The disclosed invention permits multiple broadcasts to be queued at the individual switching apparatus which resolves the broadcast contention on a synchronous priority driven basis that permits one broadcast to follow the other at the earliest possible moment and the quickest possible speed. In addition, the present invention permits multiple multi-cast operations to occur simultaneously within in the network. This is becoming an increasingly important function for future massively parallel processors consisting of many nodes that can be subdivided into many tasks. The multi-cast function permits subsets of nodes assigned to the same tasks to communicate amongst themselves without involving other nodes that are not in its own subset. The present invention provides a network capable of sustaining many multi-casts simultaneously, thus, providing a very powerful tool for future parallel applications. In accordance with our inventions, we provide hardware circuitry for the detection and correction of deadlock conditions in the multi-stage network. Deadlock conditions are not expected to be usual conditions in the network, but there is a possibility of their occurrence resulting from multiple simultaneous broadcasts or multi-casts colliding within the network in a manner which is not resolvable. The hardware circuitry detects all the different types of deadlock conditions automatically and issues correction indications to the network paths involved. The network deadlock is thereby eliminated, and the two broadcasts or multi-casts involved continue their operation in a rearranged sequence that will not cause deadlock.

摘要翻译： 公开了一种双重优先级切换装置，用于使得输入端口以任何一个输入端口至任何一个输出端口的标准模式快速且动态地输出端口连接，以多播模式从任何 一个输入端口同时进入多个输出端口的固定数量的子集，或者以广播模式从任何一个输入端口同时传输到所有输出端口，使用新的高优先级方法来解决广播或多播竞争 在输入端口之间。 所公开的优先广播和多播功能提供了更复杂，更快和更高功率的广播和多播功能。 所公开的发明允许在单个交换设备上排队多个广播，其在同步优先级驱动的基础上解决广播争用，允许一个广播在最早的可能时刻和最快的可能速度下跟随另一个广播。 此外，本发明允许多个多播操作同时发生在网络内。 这对于将来可能被细分为许多任务的许多节点组成的未来的大规模并行处理器正在成为日益重要的功能。 多播功能允许分配给相同任务的节点的子集在它们之间通信，而不涉及不在其自己的子集中的其他节点。 本发明提供了能够同时维持许多多播的网络，从而为将来的并行应用提供非常强大的工具。 根据我们的发明，我们提供用于检测和校正多级网络中的死锁状况的硬件电路。 死锁条件不被认为是网络中的通常情况，但是存在由多个同时广播或多播在网络中以不可解决的方式进行冲突的可能性。 硬件电路自动检测所有不同类型的死锁状态，并对所涉及的网络路径发出校正指示。 因此，网络死锁被消除，并且涉及的两个广播或多播将继续以重新排列的顺序进行操作，这将不会导致死锁。

公开(公告)号：EP0505780A3

公开(公告)日：1993-11-03

申请号：EP92103747.9

申请日：1992-03-05

申请人： International Business Machines Corporation

发明人： Olnowich, Howard Thomas ,  Barker, Thomas Norman ,  Kogge, Peter Michael ,  Vandling III, Gilbert Clyde

IPC分类号： G06F15/16 ,  H04L12/56

CPC分类号： H04L1/0057 ,  G06F11/261 ,  G06F13/4022 ,  G06F15/17375 ,  G06F15/17393 ,  H04L7/0338 ,  H04L12/1881 ,  H04L49/15 ,  H04L49/1523 ,  H04L49/201 ,  H04L49/205 ,  H04Q11/0066 ,  H04Q11/0478

摘要： Disclosed is a dual priority switching apparatus for making input port to output port connections on a requested basis quickly and dynamically, in a standard mode from any one of the input ports to any one of the output ports, in a multi-cast mode from any one of the input ports to a fixed number of subsets of multiple output ports simultaneously, or in a broadcast mode from any one of the input ports to all output ports simultaneously, using a new high priority approach to resolve either broadcast or multi-cast contention amongst input ports. The disclosed priority broadcast and multi-cast functions provide a more complex, yet faster and higher powered broadcast and multi-cast function. The disclosed invention permits multiple broadcasts to be queued at the individual switching apparatus which resolves the broadcast contention on a synchronous priority driven basis that permits one broadcast to follow the other at the earliest possible moment and the quickest possible speed. In addition, the present invention permits multiple multi-cast operations to occur simultaneously within in the network. This is becoming an increasingly important function for future massively parallel processors consisting of many nodes that can be subdivided into many tasks. The multi-cast function permits subsets of nodes assigned to the same tasks to communicate amongst themselves without involving other nodes that are not in its own subset. The present invention provides a network capable of sustaining many multi-casts simultaneously, thus, providing a very powerful tool for future parallel applications. In accordance with our inventions, we provide hardware circuitry for the detection and correction of deadlock conditions in the multi-stage network. Deadlock conditions are not expected to be usual conditions in the network, but there is a possibility of their occurrence resulting from multiple simultaneous broadcasts or multi-casts colliding within the network in a manner which is not resolvable. The hardware circuitry detects all the different types of deadlock conditions automatically and issues correction indications to the network paths involved. The network deadlock is thereby eliminated, and the two broadcasts or multi-casts involved continue their operation in a rearranged sequence that will not cause deadlock.

公开(公告)号：EP0505779A3

公开(公告)日：1993-11-03

申请号：EP92103746.1

申请日：1992-03-05

申请人： International Business Machines Corporation

发明人： Olnowich, Howard Thomas ,  Barker, Thomas Norman ,  Kogge, Peter Michael ,  Vandling III, Gilbert Clyde

IPC分类号： G06F15/16 ,  H04L12/56

CPC分类号： H04L1/0057 ,  G06F11/261 ,  G06F13/364 ,  G06F13/4022 ,  G06F15/17375 ,  G06F15/17393 ,  H03M9/00 ,  H04L7/0338 ,  H04L7/044 ,  H04L49/101 ,  H04L49/1515 ,  H04L49/1523 ,  H04L49/201 ,  H04L49/205 ,  H04L49/40 ,  H04L49/55 ,  H04Q11/0066 ,  H04Q11/0478

摘要： Disclosed is an implementation of a high priority path that is in addition to the normal low priority path through a multi-stage switching network. The high priority path is established at the quickest possible speed because the high priority command is stored at the switch stage involved and made on a priority basis as soon as output port required becomes available. In addition, a positive feedback is given to the node establishing the connection immediately upon the making of the connection so that it may proceed at the earliest possible moment. The high priority path is capable of processing multiple high priority pending requests, and resolving the high priority contention using a snapshot register which implements a rotating priority such that no one requesting device can ever be locked out or experience data starvation. A dual priority switching apparatus with input port connections to output port connections uses an asynchronous means to resolve contention under low priority and the absence of blockage conditions, and switches automatically to a priority driven synchronous means of resolving contention under the presence of blockage and high priority conditions. The disclosed improvement to the ALL-NODE (Asynchronous, Low Latency inter-NODE) Switch permits contention to be detected and resolved on chip in either a low or high priority mode, and yet the logic implementation is extremely simple and low in gate count, so the switch design is never gate limited. The protocol requires several parallel data lines plus four control lines so that the switching apparatus can used for networks having a plurality of nodes, each node having a plurality of input and output ports, with a a multiplexer control circuit for each output port for connecting any of I inputs to any of Z outputs, where I and Z can assume any unique value greater or equal to two, and a different priority level is assigned to a function. The switch has a single physical network path element over which either a low priority or high priority path can be established.

公开(公告)号：EP0505779A2

公开(公告)日：1992-09-30

申请号：EP92103746.1

申请日：1992-03-05

申请人： International Business Machines Corporation

发明人： Olnowich, Howard Thomas ,  Barker, Thomas Norman ,  Kogge, Peter Michael ,  Vandling III, Gilbert Clyde

IPC分类号： G06F15/16 ,  H04L12/56

CPC分类号： H04L1/0057 ,  G06F11/261 ,  G06F13/364 ,  G06F13/4022 ,  G06F15/17375 ,  G06F15/17393 ,  H03M9/00 ,  H04L7/0338 ,  H04L7/044 ,  H04L49/101 ,  H04L49/1515 ,  H04L49/1523 ,  H04L49/201 ,  H04L49/205 ,  H04L49/40 ,  H04L49/55 ,  H04Q11/0066 ,  H04Q11/0478

摘要： Disclosed is an implementation of a high priority path that is in addition to the normal low priority path through a multi-stage switching network. The high priority path is established at the quickest possible speed because the high priority command is stored at the switch stage involved and made on a priority basis as soon as output port required becomes available. In addition, a positive feedback is given to the node establishing the connection immediately upon the making of the connection so that it may proceed at the earliest possible moment. The high priority path is capable of processing multiple high priority pending requests, and resolving the high priority contention using a snapshot register which implements a rotating priority such that no one requesting device can ever be locked out or experience data starvation. A dual priority switching apparatus with input port connections to output port connections uses an asynchronous means to resolve contention under low priority and the absence of blockage conditions, and switches automatically to a priority driven synchronous means of resolving contention under the presence of blockage and high priority conditions. The disclosed improvement to the ALL-NODE (Asynchronous, Low Latency inter-NODE) Switch permits contention to be detected and resolved on chip in either a low or high priority mode, and yet the logic implementation is extremely simple and low in gate count, so the switch design is never gate limited. The protocol requires several parallel data lines plus four control lines so that the switching apparatus can used for networks having a plurality of nodes, each node having a plurality of input and output ports, with a a multiplexer control circuit for each output port for connecting any of I inputs to any of Z outputs, where I and Z can assume any unique value greater or equal to two, and a different priority level is assigned to a function. The switch has a single physical network path element over which either a low priority or high priority path can be established.

摘要翻译： 公开了除了通过多级交换网络的正常低优先级路径之外的高优先级路径的实现。 高优先级路径以尽可能快的速度建立，因为高优先级命令存储在所涉及的切换阶段，并且一旦需要输出端口可用就优先进行。 另外，在建立连接时立即建立连接的节点，使得它可以在尽可能早的时刻进行正向的反馈。 高优先级路径能够处理多个高优先级待处理请求，并且使用实现旋转优先级的快照寄存器来解决高优先权争用，使得没有一个请求设备可以被锁定或经历数据不足。 具有输入端口连接到输出端口连接的双重优先级交换设备使用异步方式来在低优先级和没有阻塞条件的情况下解决争用，并且在阻塞和高优先级存在的情况下自动切换到优先级驱动的同步方式来解决争用 条件。 ALL-NODE（异步，低延迟节点）交换机的公开改进允许在低优先级或高优先级模式下在芯片上检测和解决争用，然而逻辑实现非常简单且门计数低， 所以开关设计从来不限于门限。 该协议需要几条并行数据线加上四条控制线，使得交换设备可用于具有多个节点的网络，每个节点具有多个输入和输出端口，每个输出端口具有多路复用器控制电路，用于连接任何 我输入任何Z输出，其中I和Z可以采用大于或等于2的任何唯一值，并且将不同的优先级分配给一个功能。 交换机具有单个物理网络路径元素，通过该单个物理网络路径元素可以建立低优先级或高优先级路径。