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公开(公告)号：EP0397989A2
公开(公告)日：1990-11-22
申请号：EP90105306.6
申请日：1990-03-21
CPC分类号： G06K7/10861 , G06K1/126 , G06K7/0166 , G06K19/06028 , G06K2019/06253
摘要： A single width bar code exhibiting inherent self clocking characteristics is provided so as to be particularly useful in the identification of semiconductor wafers in very large scale integrated circuit manufacturing processes. The codes described herein are robust, reliable and highly readable even in the face of relatively high variations in scanning speed. The codes are also desirably dense in terms of character representations per linear centimeter, an important consideration in semiconductor manufacturing wherein space on the chips and the wafer is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences.
摘要翻译： 提供了表现出固有自我定时特性的单宽度条形码，以便在非常大规模的集成电路制造工艺中的半导体晶片的识别中特别有用。 即使在扫描速度的相对较高的变化的情况下，这里描述的代码是鲁棒的，可靠的和高度可读性的。 代码也希望在每线性厘米的字符表示方面是密集的，这在半导体制造中是重要的考虑因素，其中芯片和晶片上的空间是非常重要的。 另外，本发明的一个优选实施例显示代码符号序列中相邻条之间的最大空格数的最小数目。
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公开(公告)号：EP0090219B1
公开(公告)日：1989-09-13
申请号：EP83102354.4
申请日：1983-03-10
发明人： Bossen, Douglas C. , Hsiao, Mu-Yue
CPC分类号： G11C29/88 , G06F11/1024
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公开(公告)号：EP0397989A3
公开(公告)日：1992-05-06
申请号：EP90105306.6
申请日：1990-03-21
CPC分类号： G06K7/10861 , G06K1/126 , G06K7/0166 , G06K19/06028 , G06K2019/06253
摘要： A single width bar code exhibiting inherent self clocking characteristics is provided so as to be particularly useful in the identification of semiconductor wafers in very large scale integrated circuit manufacturing processes. The codes described herein are robust, reliable and highly readable even in the face of relatively high variations in scanning speed. The codes are also desirably dense in terms of character representations per linear centimeter, an important consideration in semiconductor manufacturing wherein space on the chips and the wafer is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences.
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公开(公告)号：EP0090219A3
公开(公告)日：1986-12-03
申请号：EP83102354
申请日：1983-03-10
发明人： Bossen, Douglas C. , Hsiao, Mu-Yue
IPC分类号： G06F11/10
CPC分类号： G11C29/88 , G06F11/1024
摘要： Swapping of physical bits between different logical words of a memory (40) is accomplished by reference to data (46) on bad bits in the memory. Different permutation data (34) are selected to control address inputs to each bit position (12i) in a memory word so that any word with multiple uncorrectable data is changed to a correctable logical data word by placing one or more of the bad bits in the original word into another word of the memory. The swapping is done by an exclusionary process (48) which identifies and deselects certain deleterious potential combinations of actual addresses thereby limiting the selection process to ohter combinations. The process can involve categorizing (44) of failures in accordance with type, and performing (48) algorithm operations which identify combinations of bit addresses that would result in combining the failures so that there are more errors in any memory word than would be correctable by the error correction code monitoring (42) the memory.
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5.发明公开
公开(公告)号：EP0090219A2
公开(公告)日：1983-10-05
申请号：EP83102354.4
申请日：1983-03-10
发明人： Bossen, Douglas C. , Hsiao, Mu-Yue
CPC分类号： G11C29/88 , G06F11/1024
摘要： Swapping of physical bits between different logical words of a memory (40) is accomplished by reference to data (46) on bad bits in the memory. Different permutation data (34) are selected to control address inputs to each bit position (12i) in a memory word so that any word with multiple uncorrectable data is changed to a correctable logical data word by placing one or more of the bad bits in the original word into another word of the memory. The swapping is done by an exclusionary process (48) which identifies and deselects certain deleterious potential combinations of actual addresses thereby limiting the selection process to ohter combinations. The process can involve categorizing (44) of failures in accordance with type, and performing (48) algorithm operations which identify combinations of bit addresses that would result in combining the failures so that there are more errors in any memory word than would be correctable by the error correction code monitoring (42) the memory.
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