公开(公告)号：EP0300139B1

公开(公告)日：1993-07-07

申请号：EP88106199.8

申请日：1988-04-19

申请人： International Business Machines Corporation

发明人： Chen, Chin-Long

IPC分类号： H03M13/00 ,  G06F11/10

CPC分类号： G06F11/1028 ,  H03M13/19

公开(公告)号：EP0386462A2

公开(公告)日：1990-09-12

申请号：EP90102079.2

申请日：1990-02-02

申请人： International Business Machines Corporation

发明人： Blake, Robert Martin ,  Bossen, Douglas Craig ,  Chen, Chin-Long ,  Fifield, John Atkinson ,  Kalter, Howard Leo ,  Lo, Tin-Chee

IPC分类号： G06F11/00

CPC分类号： G06F11/1052 ,  G06F11/1008

摘要： In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

摘要翻译： 在包括多个存储单元（10）的存储器系统中，每个存储器单元具有单位级错误校正能力（20），并且每个存储器单元都连接到系统级错误校正功能（30），通过提供装置 用于响应于在一个存储器单元中出现不可校正的错误，将一个存储器单元的输出固定为固定值。 这种产生强制硬错误的反直觉方法仍然提高了整体存储系统的可靠性，因为它能够使用补充/重新补充算法，这取决于是否存在可重复的错误以进行正确的操作。 因此，在高封装密度下越来越需要的芯片级误差校正系统采用不干扰系统级误差校正方法的方式。

公开(公告)号：EP0300139A3

公开(公告)日：1990-05-02

申请号：EP88106199.8

申请日：1988-04-19

申请人： International Business Machines Corporation

发明人： Chen, Chin-Long

IPC分类号： H03M13/00 ,  G06F11/10

CPC分类号： G06F11/1028 ,  H03M13/19

摘要： A reduced redundancy error correction and detection code is shown for memory organized with several bits of the data word on each chip. This package error correction and detection will correct all errors on any one chip and detect errors on more than one chip. A certain arrangement of an ECC matrix is first created for a symbol size code greater than the number of bits per chip. Thereafter certain columns of the matrix are removed to create the final code having a symbol size the same as the number of bits per chip. A specific example of an 80 bit code word is shown having 66 data bits and 14 check bits for a 4-bit-per-chip memory.

公开(公告)号：EP0623887A1

公开(公告)日：1994-11-09

申请号：EP94106391.9

申请日：1994-04-25

申请人： International Business Machines Corporation

发明人： Bossen, Douglas Craig ,  Chen, Chin-Long ,  Doany, Fuad Elias ,  Hsiao, Mu-Yue ,  Rand, Ricky Allen ,  Terbruggen, Ralf Joachim

IPC分类号： G06K1/12 ,  G06K15/00 ,  G06K19/08

CPC分类号： G06K1/126 ,  G06K15/22 ,  Y10S235/90

摘要： A method and apparatus is provided for producing single width barcodes in a continuous, serpentine pattern. This pattern provides continuity of operation for laser marking instruments and thereby results in the formation of more uniform and higher quality barcode indicia. The use of a continuous serpentine pattern also increases the speed at which the code may be written onto a substrate. This marking method is particularly appropriate for use in marking a wide variety of materials including semiconductors, metals, plastics and ceramics.

摘要翻译： 提供了一种用于以连续的蛇形图案生产单个宽度条形码的方法和装置。 这种图案为激光打标仪提供连续的操作，从而形成更均匀和更高质量的条形码标记。 连续蛇形图案的使用也增加了代码可写入基板的速度。 该标记方法特别适用于标记各种材料，包括半导体，金属，塑料和陶瓷。

公开(公告)号：EP0386461A3

公开(公告)日：1991-10-23

申请号：EP90102078.4

申请日：1990-02-02

申请人： International Business Machines Corporation

发明人： Blake, Robert Martin ,  Bossen, Douglas Craig ,  Chen, Chin-Long ,  Fifield, John Atkinson ,  Kalter, Howard Leo

IPC分类号： G06F11/00

CPC分类号： G06F11/1052 ,  G06F11/1008

摘要： In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：EP0397989A2

公开(公告)日：1990-11-22

申请号：EP90105306.6

申请日：1990-03-21

申请人： International Business Machines Corporation

发明人： Bossen, Douglas C. ,  Chen, Chin-Long ,  Dill, Frederick H. ,  Goodman, Douglas S.

IPC分类号： G06K7/016 ,  G06K7/10 ,  G06K19/06

CPC分类号： G06K7/10861 ,  G06K1/126 ,  G06K7/0166 ,  G06K19/06028 ,  G06K2019/06253

摘要： A single width bar code exhibiting inherent self clocking characteristics is provided so as to be particularly useful in the identification of semi­conductor wafers in very large scale integrated circuit manufacturing processes. The codes described herein are robust, reliable and highly readable even in the face of relatively high variations in scanning speed. The codes are also desirably dense in terms of character representations per linear centimeter, an important consideration in semiconductor manufacturing wherein space on the chips and the wafer is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences.

摘要翻译： 提供了表现出固有自我定时特性的单宽度条形码，以便在非常大规模的集成电路制造工艺中的半导体晶片的识别中特别有用。 即使在扫描速度的相对较高的变化的情况下，这里描述的代码是鲁棒的，可靠的和高度可读性的。 代码也希望在每线性厘米的字符表示方面是密集的，这在半导体制造中是重要的考虑因素，其中芯片和晶片上的空间是非常重要的。 另外，本发明的一个优选实施例显示代码符号序列中相邻条之间的最大空格数的最小数目。

公开(公告)号：EP0188192B1

公开(公告)日：1992-04-15

申请号：EP86100031.3

申请日：1986-01-02

申请人： International Business Machines Corporation

发明人： Arlington, David L. ,  Chen, Chin-Long ,  Evans, Edward K.

IPC分类号： H03M13/00 ,  G06F11/10

CPC分类号： G06F11/1028 ,  G11B2020/183 ,  H03M13/033 ,  H03M13/19

摘要： An extended error code particularly applicable to a code that can correct any number of errors in one sub-field but can only detect the existence of any number of errors in two sub-fields. If the initial pass of the data through the error correction code indicates an uncorrected error, the data is complemented and restored in the memory and then reread. The retrieved data is recomplemented and again passed through the error correction code. If an uncorrected error persists, then a bit-by-bit comparision is performed between the originally read data and the retrieved complemented data to isolate the hard fails in the memory. The bits in the sub-field associated with the hard fail are then sequentially changed and then the changed data word is passed through the error correction code. A wrong combination is detected by the error correction code. The sequential changing continues until the bits in the sub-field associated with the hard fail match the originally stored data, in which case the error correction code can correct the remaining errors in the remaining sub-fields.

公开(公告)号：EP0405099A2

公开(公告)日：1991-01-02

申请号：EP90108765.0

申请日：1990-05-10

申请人： International Business Machines Corporation

发明人： Bossen, Douglas Craig ,  Chen, Chin-Long ,  Hsiao, My-Yue

IPC分类号： H03M13/00 ,  G06K5/00

CPC分类号： H03M13/07 ,  G06K19/14

摘要： An error correction coding system employs a single check symbol from an arbitrary sequence of information symbols to provide single error correction at the symbol level. The sequence of information symbols may in fact also be arbitrarily long. The coding system of the present invention provides both a method and apparatus for encoding the check symbol and a method and apparatus for error correction based upon the single coded symbol character. The system is particularly applicable for use in conjunction with bar code recognition systems but is in fact applicable to a broad range of coding systems, including optical character recognition and ordinary alphanumeric codes.

摘要翻译： 纠错编码系统采用来自任意信息符号序列的单个检查符号，以在符号级提供单个纠错。 信息符号的序列实际上也可以是任意长的。 本发明的编码系统提供了用于对该校验符号进行编码的方法和装置以及用于基于单个编码符号字符进行纠错的方法和装置。 该系统特别适用于与条形码识别系统结合使用，但实际上适用于广泛的编码系统，包括光学字符识别和普通字母数字代码。

公开(公告)号：EP0386506A2

公开(公告)日：1990-09-12

申请号：EP90103034.6

申请日：1990-02-16

申请人： International Business Machines Corporation

发明人： Chen, Chin-Long

IPC分类号： H03M13/00

CPC分类号： H03M13/13

摘要： Byte or symbol organized linear block codes are optimized in terms of reducing the number of ones in their parity check matrices by means of symbol column transformations carried out by multiplication by non-singular matrices. Each optimized symbol column preferably, and probably necessarily, includes a submatrix which is the identity matrix which contributes to low weight check matrices and also to simplified decoding procedures and apparatus. Since circuit cost and layout area are proportional to the number of Exclusive-OR gates which is determined by the number of ones in the check matrix, it is seen that the reduction procedures carried out in accordance with the present invention solve significant problems that are particularly applicable in the utilization of byte organized semiconductor memory systems. Reduced weight coding systems are also generated in accordance with weight reducing procedures used in conjunction with modified Reed Solomon codes. The decoding and encoding methods and apparatus are extendable to the inclusion of any number of check symbols.

摘要翻译： 通过利用非奇异矩阵乘法执行的符号列变换，减少奇偶校验矩阵中的字节或符号组织线性块码的优化。 每个优化的符号列优选并且可能必须包括作为有助于低权重校验矩阵的单位矩阵的子矩阵，以及简化的解码过程和装置。 由于电路成本和布局面积与由校验矩阵中的数量确定的异或门的数量成比例，可以看出，根据本发明执行的还原过程解决了特别是 适用于使用字节有组织的半导体存储器系统。 根据与修改的里德所罗门码一起使用的减重程序也产生了减重编码系统。 解码和编码方法和装置可扩展到包含任何数量的校验符号。

公开(公告)号：EP0300139A2

公开(公告)日：1989-01-25

申请号：EP88106199.8

申请日：1988-04-19

申请人： International Business Machines Corporation

发明人： Chen, Chin-Long

IPC分类号： H03M13/00 ,  G06F11/10

CPC分类号： G06F11/1028 ,  H03M13/19

摘要： A reduced redundancy error correction and detection code is shown for memory organized with several bits of the data word on each chip. This package error correction and detection will correct all errors on any one chip and detect errors on more than one chip. A certain arrangement of an ECC matrix is first created for a symbol size code greater than the number of bits per chip. Thereafter certain columns of the matrix are removed to create the final code having a symbol size the same as the number of bits per chip. A specific example of an 80 bit code word is shown having 66 data bits and 14 check bits for a 4-bit-per-chip memory.

摘要翻译： 对于每个芯片上的数据字的几个位组织的存储器，示出了减少的冗余错误校正和检测码。 该包纠错和检测将纠正任何一个芯片上的所有错误，并检测多个芯片上的错误。 首先针对大于每个芯片的位数的符号大小代码创建ECC矩阵的某种布置。 此后，除去矩阵的某些列以创建具有与每个芯片的位数相同的符号大小的最终代码。 显示了一个80位代码字的具体示例，其具有66位数据位和14位每位芯片存储器的校验位。