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公开(公告)号：EP0142766A2
公开(公告)日：1985-05-29
申请号：EP84113322.6
申请日：1984-11-06
IPC分类号： H03K19/173 , H03K19/094
CPC分类号： H03K19/0948 , H01L27/112
摘要： A method is provided for reducing an arbitrary Boolean logic expression to static CMOS circuits by the use of a general matrix (10 and 12) of P channel devices and N channel devices which are interconnected in accordance with the terms of Boolean logic expressions derived from a truth table. More specifically, from a Boolean expression a sum-of-products expression giving the 1 binary data outputs of a truth table having a 0 input is found. This is accomplished by complementing, or barring, the literals which are a binary 1 when the output is 1 and leaving true or unbarred the literals that are a binary 0. Then each input (A-D; A-D) of a given product term is applied to the control gate of a P channel device, which devices are connected in series with one end tied to a source of potential (V H ) and the other end of the series circuit connected to an output terminal (Q). Each product term is arranged in parallel with other channel device series circuits to form one half of a complete logic matrix (10). Similarly, for the other halfofthe matrix (12), a sum-of-products expression giving the binary 0 outputs of a truth table having a binary 1 for an input is found. Each input of a given product term is applied to the control gate of an N channel device, which devices are connected in series with one end tied to a potential reference point, such as ground, and the other end of the series circuit is connected to the output terminal. Each product term is arranged in parallel with other N channel device series circuits.
摘要翻译： 提供了一种通过使用P通道器件和N沟道器件的通用矩阵（10和12）将静态CMOS电路的任意布尔逻辑表达式减少的方法，该通道器件和N沟道器件根据从 真相表。 更具体地，从布尔表达式中，找到给出具有0输入的真值表的1个二进制数据输出的乘积和表达式表达式。 这是通过补充或限制当输出为1并且将真实或未标记为二进制0的字面值作为二进制1的文字时实现的。然后将给定产品项的每个输入（AD; AD）应用于 P沟道器件的控制栅极，这些器件与连接到电位源（VH）的一端串联连接，而串联电路的另一端连接到输出端（Q）。 每个产品术语与其他P通道器件串联电路并联布置以形成完整逻辑矩阵（10）的一半。 类似地，对于矩阵（12）的另一半，找到给出具有用于输入的二进制1的真值表的二进制0输出的积和表达式。 给定产品项的每个输入被施加到N沟道器件的控制栅极，这些器件与连接到电位参考点（例如地）的一端串联连接，并且串联电路的另一端连接到 输出端子。 每个产品术语与其他N通道器件串联电路并联布置。
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公开(公告)号：EP0024311A3
公开(公告)日：1982-09-01
申请号：EP80104358
申请日：1980-07-24
发明人： Fortino, Andreas Guillermo , Geipel, Henry John jr. , Heller, Lawrence Griffith , Silverman, Ronald
CPC分类号： H01L27/11266 , G11C11/56 , G11C11/5692 , G11C17/12 , H01L21/2253 , H01L27/112
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公开(公告)号：EP0024311B1
公开(公告)日：1986-06-18
申请号：EP80104358.9
申请日：1980-07-24
发明人： Fortino, Andreas Guillermo , Geipel, Henry John jr. , Heller, Lawrence Griffith , Silverman, Ronald
CPC分类号： H01L27/11266 , G11C11/56 , G11C11/5692 , G11C17/12 , H01L21/2253 , H01L27/112
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公开(公告)号：EP0074480A2
公开(公告)日：1983-03-23
申请号：EP82106649.5
申请日：1982-07-23
IPC分类号： G11C11/56
CPC分类号： G11C11/404 , G11C11/565 , G11C27/024 , Y10S257/92
摘要： A dense memory is provided which includes a one device random access memory cell using charge fill and spill techniques wherein a potential well under a storage node is filled with charge and the excess charge above a predetermined level is spilled to a diffusion or drain region connected to a sense line through a channel region controlled by pulses on a word line. One bit or two or more bits of information may be stored in the potential well at any given instant of time. Depending upon the value of the increment of voltage applied to the storage node or electrode, a given analog charge packet is stored in a potential well formed under the storage electrode. Information is read by applying a voltage to the word line to turn on the channel region and then stepping down the voltage on the storage electrode in fractional, preferably one half, increments. Charge from a charge packet spilled from the potential well under the storage electrode is detected by a sensing circuit connected to the sense line. To rewrite information into the potential well, the original increment of voltage is applied to the storage node and the sense line is pulled to ground so that the diffusion region acts as a source of charge for the potential well.
摘要翻译： 提供密集存储器，其包括使用电荷填充和溢出技术的一个器件随机存取存储器单元，其中存储节点下方的势阱被电荷填充，并且超过预定电平的过量电荷被溅射到连接到 通过由字线上的脉冲控制的沟道区域的感测线。 一位或两位或更多位的信息可以在任何给定的时刻存储在势阱中。 根据施加到存储节点或电极的电压增量的值，给定的模拟电荷包存储在存储电极下形成的势阱中。 通过向字线施加电压来打开信道区域，然后逐步降低存储电极上的电压，最好以一半的增量逐步降低信息。 来自从存储电极下方的势阱溢出的电荷包的电荷由连接到感测线的感测电路检测。 为了将信息重写到势阱中，电压的原始增量被施加到存储节点并且感测线被拉到地，使得扩散区域充当势阱的电荷源。
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公开(公告)号：EP0031491A2
公开(公告)日：1981-07-08
申请号：EP80107619.1
申请日：1980-12-04
IPC分类号： G11C11/24
CPC分类号： G11C11/565 , G11C7/06 , G11C11/4091 , G11C19/36
摘要： A calibrated sensing system is provided for sensing charge in a storage medium, such as a storage capacitor (16), coupled to an access or bit/sense line (B/S) which compensates for most sources of variability in the storage medium and in the access line. In the system, the unknown charge stored in the storage medium is transferred to a first capacitor (28) or potential well via the access line. A high charge state of the storage medium is written into the storage medium and known fractional packets of charge are prepared therefrom, transferred selectively to a second capacitor (30) or potential well and compared with the unknown charge in the first potential well to determine the relative level of the unknown charge that was stored in the storage medium. By selectively using two or more fractional packets of charge multilevel sensing is performed.
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公开(公告)号：EP0008691A1
公开(公告)日：1980-03-19
申请号：EP79102846.7
申请日：1979-08-07
IPC分类号： H01L27/10 , H01L21/82 , H01L21/265 , H01L27/06
CPC分类号： H01L27/0733 , H01L21/2652 , H01L21/823406 , H01L27/1055
摘要： Die Erfindung betrifft eine Anordnung und ein Verfahren zum Herstellen einer sogenannten Eimerkettenschaltung durch eine Vereinigung eines MOS-Kondensators mit einem Metalloxide-Silicium-Feldeffekttransistor zur Bildung einer Ladungsübertragungszelle. In einem Teil einer P-leitenden Kanalzone eines Feldeffekttransistors wird anschließend an die Draindiffusionszone (104) eine dünne N-leitende Zone (107) mit einer ersten Konzentration durch Ionenimplantation hergestellt. Anschließend an die erste durch Ionenimplantation hergestellte Zone (107) wird eine zweite Zone (113) durch Ionenimplantation mit einem N-Leitung hervorrufenden Störelement mit einer zweiten Konzentration eingebracht, die geringer ist als die erste Konzentration. Die N-leitende Konzentration in der zweiten Zone (113) reicht gerade dazu aus, die P-leitende Hintergrunddotierung in der Kanalzone zu kompensieren. Durch diese Struktur wird der Ladungsübertragungswirkungsgrad für die Zelle erhöht, während gleichzeitig die Abhängigkeit der Schwellenwertspannung von der Source- und Drain- spannung verringert wird. Die Gateelektrode (112) der Zelle weist eine wesentliche Überlappung über der Drainzone und eine minimale Überlappung über der Sourcezone auf, und die Drain-Gate-Kapazität je Flächeneinheit wird dadurch zu einem Maximum gemacht, daß eine gleichförmig dünne Oxidschicht (110) über der Gatezone beibehalten wird.
摘要翻译： 1.一种用于所谓的桶式装置的存储单元，具有这种单元的串联连接的序列，包括具有第一导电类型的半导体衬底（102）和用于第一单元的源极区域（104'），第二 具有预定厚度的导电类型，用于该单元的第二导电类型的漏极区（104），与源极区隔开，具有第一掺杂剂浓度和预测厚度，还包括第一离子注入漏极区域（107） ），所述第二导电类型的第二导电类型具有小于第一掺杂剂浓度的第二掺杂剂浓度，以及小于位于漏区和源极区之间的源区和漏区的厚度的厚度， 紧邻漏极区域，以及位于通道和第一离子注入漏极区域（107）上的位于衬底（2）的表面上的薄绝缘层（110），厚度为 位于源极和漏极区域（104）上的衬底表面上的绝缘层（106）和位于薄绝缘层（110）之上的栅电极（112），其特征在于，紧邻第一离子 - 具有第二掺杂剂浓度的第二导电类型的注入漏极区域（107），具有第二导电类型的第二离子注入漏极区域（113）具有小于第二掺杂剂浓度的第三掺杂剂浓度 ，所述第二离子注入漏极区域与第一源极区域间隔开并且具有小于第一离子注入漏极区域的厚度，使得所得结构构成具有不同阈值的两个组合FET元件，其作为电荷存储器 具有场效应晶体管的电容器形成存储单元。
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公开(公告)号：EP0031491B1
公开(公告)日：1986-12-03
申请号：EP80107619.1
申请日：1980-12-04
IPC分类号： G11C11/24
CPC分类号： G11C11/565 , G11C7/06 , G11C11/4091 , G11C19/36
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公开(公告)号：EP0142766A3
公开(公告)日：1986-07-23
申请号：EP84113322
申请日：1984-11-06
IPC分类号： H03K19/173 , H03K19/094
CPC分类号： H03K19/0948 , H01L27/112
摘要： A method is provided for reducing an arbitrary Boolean logic expression to static CMOS circuits by the use of a general matrix (10 and 12) of P channel devices and N channel devices which are interconnected in accordance with the terms of Boolean logic expressions derived from a truth table. More specifically, from a Boolean expression a sum-of-products expression giving the 1 binary data outputs of a truth table having a 0 input is found. This is accomplished by complementing, or barring, the literals which are a binary 1 when the output is 1 and leaving true or unbarred the literals that are a binary 0. Then each input (A-D; A-D) of a given product term is applied to the control gate of a P channel device, which devices are connected in series with one end tied to a source of potential (V H ) and the other end of the series circuit connected to an output terminal (Q). Each product term is arranged in parallel with other channel device series circuits to form one half of a complete logic matrix (10). Similarly, for the other halfofthe matrix (12), a sum-of-products expression giving the binary 0 outputs of a truth table having a binary 1 for an input is found. Each input of a given product term is applied to the control gate of an N channel device, which devices are connected in series with one end tied to a potential reference point, such as ground, and the other end of the series circuit is connected to the output terminal. Each product term is arranged in parallel with other N channel device series circuits.
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公开(公告)号：EP0074480A3
公开(公告)日：1986-02-05
申请号：EP82106649
申请日：1982-07-23
IPC分类号： G11C11/56
CPC分类号： G11C11/404 , G11C11/565 , G11C27/024 , Y10S257/92
摘要： A dense memory is provided which includes a one device random access memory cell using charge fill and spill techniques wherein a potential well under a storage node is filled with charge and the excess charge above a predetermined level is spilled to a diffusion or drain region connected to a sense line through a channel region controlled by pulses on a word line. One bit or two or more bits of information may be stored in the potential well at any given instant of time. Depending upon the value of the increment of voltage applied to the storage node or electrode, a given analog charge packet is stored in a potential well formed under the storage electrode. Information is read by applying a voltage to the word line to turn on the channel region and then stepping down the voltage on the storage electrode in fractional, preferably one half, increments. Charge from a charge packet spilled from the potential well under the storage electrode is detected by a sensing circuit connected to the sense line. To rewrite information into the potential well, the original increment of voltage is applied to the storage node and the sense line is pulled to ground so that the diffusion region acts as a source of charge for the potential well.
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10.发明公开Clocked differential cascode voltage switch logic circuit 失效Getaktete Logische Schaltung mit Spannungsschaltern在Differential-Kaskoden-Schaltung。
公开(公告)号：EP0147598A1
公开(公告)日：1985-07-10
申请号：EP84113734.2
申请日：1984-11-14
IPC分类号： H03K19/096
CPC分类号： H03K19/1738
摘要： A clocked differential cascode voltage switch (CVS) logic system is provided for a complete logic family which has a first switching circuit (10) that produces a given output signal at a first output node (14) and a second switching circuit (12) that produces a second output signal which is the complement of that of the given output signal at a second output node (18). First and second clocked devices (24, 28) are connected from the first and second output nodes (14, 18), respectively, to a voltage source (V H ), the first and second inverters (32,34) are connected to the first and second output nodes (14, 18), respectively. Additionally, a regenerative circuit (26, 30) may be connected between the first and second output nodes (14, 18) and the voltage source (V H ).
摘要翻译： 提供了一种用于完整逻辑系列的时钟差分级联开关电压开关（CVS）逻辑系统，其具有在第一输出节点（14）和第二开关电路（12）处产生给定输出信号的第一开关电路（10），第二开关电路 产生第二输出信号，其是在第二输出节点（18）处的给定输出信号的补码的补码。 第一和第二时钟装置（24,28）分别从第一和第二输出节点（14,18）连接到电压源（VH），第一和第二反相器（32,34）连接到第一和第二输出节点 和第二输出节点（14,18）。 此外，再生电路（26,30）可以连接在第一和第二输出节点（14,18）和电压源（VH）之间。
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