公开(公告)号：EP3007347A3

公开(公告)日：2016-07-20

申请号：EP15002646.6

申请日：2015-09-10

申请人： Infineon Technologies AG

发明人： Ahlers, Dirk ,  Auer, Frank ,  Gietler, Herbert ,  Lenz, Michael

IPC分类号： H02M7/219 ,  H02M1/08 ,  H01L27/088 ,  H02M1/00

CPC分类号： H02M1/08 ,  H01L27/0207 ,  H01L27/0733 ,  H02K11/046 ,  H02M7/217 ,  H02M7/219 ,  H02M2001/0048 ,  H02M2007/2195 ,  Y02B70/1408

摘要： A rectifying device includes a power transistor and a gate control circuit and a capacitor structure arranged on a single semiconductor die. The power transistor includes a source or emitter terminal connected to a first terminal of the rectifying device, a drain or collector terminal connected to a second terminal of the rectifying device, and a gate. The gate control circuit is configured for controlling a (the) gate voltage at the gate of the power transistor based on at least one parameter relating to at least one of a voltage and a current between the first terminal and the second terminal.

摘要翻译： 整流装置包括设置在单个半导体管芯上的功率晶体管和栅极控制电路以及电容器结构。 功率晶体管包括连接到整流装置的第一端子的源极或发射极端子，连接到整流装置的第二端子的漏极或集电极端子以及栅极。 栅极控制电路被配置用于基于与第一端子和第二端子之间的电压和电流中的至少一个有关的至少一个参数来控制功率晶体管的栅极处的（）栅极电压。

公开(公告)号：EP3007347A2

公开(公告)日：2016-04-13

申请号：EP15002646.6

申请日：2015-09-10

申请人： Infineon Technologies AG

发明人： Ahlers, Dirk ,  Auer, Frank ,  Gietler, Herbert ,  Lenz, Michael

IPC分类号： H02M7/219

CPC分类号： H02M1/08 ,  H01L27/0207 ,  H01L27/0733 ,  H02K11/046 ,  H02M7/217 ,  H02M7/219 ,  H02M2001/0048 ,  H02M2007/2195 ,  Y02B70/1408

摘要： A rectifying device includes a power transistor and a gate control circuit and a capacitor structure arranged on a single semiconductor die. The power transistor includes a source or emitter terminal connected to a first terminal of the rectifying device, a drain or collector terminal connected to a second terminal of the rectifying device, and a gate. The gate control circuit is configured for controlling a (the) gate voltage at the gate of the power transistor based on at least one parameter relating to at least one of a voltage and a current between the first terminal and the second terminal.

摘要翻译： 整流装置包括功率晶体管和布置在单个半导体管芯上的栅极控制电路和电容器结构。 功率晶体管包括连接到整流装置的第一端子的源极或发射极端子，连接到整流装置的第二端子的漏极或集电极端子以及栅极。 栅极控制电路被配置为基于与第一端子和第二端子之间的电压和电流中的至少一个有关的至少一个参数来控制功率晶体管的栅极处的栅极电压。

公开(公告)号：EP2555241A1

公开(公告)日：2013-02-06

申请号：EP11176349.6

申请日：2011-08-02

申请人： NXP B.V.

发明人： Rutter, Phil

IPC分类号： H01L27/07 ,  H01L29/78

CPC分类号： H01L29/66666 ,  H01L25/072 ,  H01L27/0733 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is an IC die and a semiconductor package (10) comprising such an IC die. The package comprises a first voltage terminal (12), a second voltage terminal (14), a first die comprising a first MOSFET (100) having a drain region (102) electrically connected to the first voltage terminal and further having a source region; and a second die adjacent to the first die, the second die comprising a second MOSFET (100') having a drain region electrically connected to the source region of the first MOSFET and having a source region electrically connected to the second voltage terminal, wherein the semiconductor package further comprises a vertical capacitor (200) having a first plate (202) electrically connected to the drain region of the first MOSFET and a second plate (206) electrically connected to the source region of the second MOSFET and being electrically insulated from the first plate by a dielectric material (204), said capacitor being integrated on the first die or the second die. A printed circuit board and a method for manufacturing the IC die are also disclosed.

摘要翻译： 公开了一种IC，并且半导体封装（10）包括寻求IC这一点。 该包装包括一个第一电压端子（12），第二电压端子（14），第一，包含一个第一MOSFET（100），具有一个漏极区域102电连接到所述第一电压端子和另外具有源极区; 和第二，相邻于所述第一，所述，第二个包括具有漏区电连接到所述第一MOSFET的源极区域和具有源极区电连接到所述第二电压端子，worin所述第二MOSFET（100“） 半导体封装还包括垂直电容器200，其具有第一板（202）电连接到所述第一MOSFET的漏极区域和第二板（206）电连接到所述第二MOSFET的源极区和在电气上与绝缘 由电介质材料（204）的第一板，所述电容器被集成在第一或第二中所述。 一种印刷电路板及其制造集成电路的方法，从而在盘被游离缺失，

公开(公告)号：EP2965354A1

公开(公告)日：2016-01-13

申请号：EP14707606.1

申请日：2014-02-19

申请人： Qualcomm Incorporated

发明人： LI, Xia ,  YANG, Bin

IPC分类号： H01L23/522 ,  H01L27/07 ,  H01L29/94 ,  H01L49/02

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L27/0733 ,  H01L28/88 ,  H01L28/92 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： A particular metal-oxide-metal (MOM) capacitor device includes a conductive gate material coupled to a substrate. The MOM capacitor device further includes a first metal structure coupled to the conductive gate material. The MOM capacitor device further includes a second metal structure coupled to the substrate and proximate to the first metal structure.

摘要翻译： 特定的金属氧化物金属（MOM）电容器器件包括耦合到衬底的导电栅极材料。 MOM电容器装置还包括耦合到导电栅极材料的第一金属结构。 MOM电容器装置还包括耦合到衬底并且靠近第一金属结构的第二金属结构。

公开(公告)号：EP1586118B1

公开(公告)日：2008-10-08

申请号：EP04701373.5

申请日：2004-01-12

申请人： STMicroelectronics S.A.

发明人： SCHOELLKOPF, Jean-Pierre

IPC分类号： H01L27/11

CPC分类号： H01L28/60 ,  H01L27/0733 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/945

摘要： The invention concerns a capacitor whereof one first electrode consists of a highly doped active region (D) of a semiconductor component (T) formed on one side of a surface of a semiconductor body, and whereof the second electrode consists of a conductive region (BR) coated with insulation (IL) formed beneath said active region and embedded in the semiconductor body.

公开(公告)号：EP0008691B1

公开(公告)日：1982-07-07

申请号：EP79102846.7

申请日：1979-08-07

申请人： International Business Machines Corporation

发明人： Heller, Lawrence Griffith ,  Jones, Harry Jordan ,  Kotecha, Harish N. ,  Soderman, Donald Arvid

IPC分类号： H01L27/10 ,  H01L21/82 ,  H01L21/265 ,  H01L27/06

CPC分类号： H01L27/0733 ,  H01L21/2652 ,  H01L21/823406 ,  H01L27/1055

公开(公告)号：EP0032279A1

公开(公告)日：1981-07-22

申请号：EP80300114.8

申请日：1980-01-11

申请人： MOSTEK CORPORATION

发明人： Chan, Tsiu Chiu

IPC分类号： H01L27/10 ,  H01L27/06 ,  G11C11/24

CPC分类号： H01L27/0733 ,  G11C11/404 ,  H01L27/10805

摘要： An integrated circuit memory cell pair having its data lines (30) (32) (34) insulated with respect to the semiconductor substrate (70)at all points other than the point of electrical contact (62) to the transistors of each memory cell. The semiconductor substrate has drain and source regions (12) (18) (22) (28) about the transmission channel of the field effect transistor and has a first capacitor electrode integral with one terminal of the transistor. A first polysilicon layer (82) insulatively disposed relative to the substrate provides a conductive layer for a second capacitor electrode for each memory cell. A second insulatively disposed polysilicon layer (86) provides the gate regions (16) (26) of the transistors and the data lines. The data lines make electrical contact through a self-aligned embedded contact. Using this construction, a highly dense memory cell array is achieved without sacrificing capacitor area.

摘要翻译： 在除了每个存储单元的晶体管的电触点（62）以外的所有点处，具有相对于半导体衬底（70）绝缘的数据线（30）（32）（34）的集成电路存储单元对。 半导体衬底具有围绕场效应晶体管的透射通道的漏极和源极区（12）（18）（22）（28），并且具有与晶体管的一个端子成一体的第一电容器电极。 相对于基板绝缘地布置的第一多晶硅层（82）为每个存储单元提供用于第二电容器电极的导电层。 第二绝配布置的多晶硅层（86）提供晶体管和数据线的栅极区域（16）（26）。 数据线通过自对准嵌入式触点进行电接触。 使用这种结构，在不牺牲电容器面积的情况下实现高密度存储单元阵列。

公开(公告)号：EP3072170A1

公开(公告)日：2016-09-28

申请号：EP14780735.8

申请日：2014-09-23

申请人： Qualcomm Incorporated

发明人： LEE, Bruce Sokki ,  BAZARJANI, Seyfollah Seyfollahi ,  DAI, Liang

IPC分类号： H01L49/02 ,  H01L23/522 ,  H01L27/07

CPC分类号： H01L27/0629 ,  H01L23/5223 ,  H01L27/0733 ,  H01L28/60 ,  H01L28/86 ,  H01L28/92 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

摘要： A methods for fabricating a capacitor structure includes fabricating polysilicon structures (PO) on a semiconductor substrate. The method further includes fabricating Ml to diffusion (MD) interconnects on the semiconductor substrate. The polysilicon structures are disposed in an interleaved arrangement with the MD interconnects. The method also includes selectively connecting the interleaved arrangement of the MD interconnects and/or the polysilicon structures as the capacitor structure.

公开(公告)号：EP3046140A3

公开(公告)日：2016-08-10

申请号：EP16150741.3

申请日：2016-01-11

申请人： Renesas Electronics Corporation

发明人： KAWAI, Tohru ,  NAKASHIBA, Yasutaka ,  AKIYAMA, Yutaka

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/739 ,  H01L27/07

CPC分类号： H01L29/7813 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0733 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

摘要翻译： 在不增加半导体芯片面积的情况下提高了半导体器件的性能。 例如，功率晶体管的源电极和电容器元件的上电极具有重叠部分。 换句话说，电容器元件的上电极通过电容器绝缘膜形成在功率晶体管的源电极上。 即，功率晶体管和电容器元件在半导体芯片的厚度方向上层叠配置。 其结果是，能够抑制半导体芯片的平面尺寸的增加，并且追加与功率晶体管电连接的电容元件。

公开(公告)号：EP3046140A2

公开(公告)日：2016-07-20

申请号：EP16150741.3

申请日：2016-01-11

申请人： Renesas Electronics Corporation

发明人： KAWAI, Tohru ,  NAKASHIBA, Yasutaka ,  AKIYAMA, Yutaka

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/739

CPC分类号： H01L29/7813 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0733 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

摘要翻译： 在不增加半导体芯片的面积尺寸的情况下，半导体器件的性能得到改善。 例如，功率晶体管的源电极和电容器元件的上电极具有重叠部分。 换句话说，电容器元件的上电极通过电容器绝缘膜形成在功率晶体管的源极上。 也就是说，功率晶体管和电容器元件在半导体芯片的厚度方向上层叠。 结果，可以在抑制半导体芯片的平面尺寸的增加的同时添加电耦合到功率晶体管的电容器元件。