摘要:
The aluminum/copper alloy conductors are made by forming a patterned layer of copper (21) on a layer of aluminum (15) applied to a substrate (11) The portion of the aluminum layer (15) which is not protected by the copper layer (21) is removed by reactive ion etching without heating substrate (11) and the resulting structure is then heated to cause the copper (21) to diffuse into, and alloy with the aluminum layer (15). The method can in particular be used to form aluminum/ copper alloy conductor lands in integrated circuit manufacture.
摘要:
The aluminum/copper alloy conductors are made by forming a patterned layer of copper (21) on a layer of aluminum (15) applied to a substrate (11) The portion of the aluminum layer (15) which is not protected by the copper layer (21) is removed by reactive ion etching without heating substrate (11) and the resulting structure is then heated to cause the copper (21) to diffuse into, and alloy with the aluminum layer (15). The method can in particular be used to form aluminum/ copper alloy conductor lands in integrated circuit manufacture.
摘要:
Disclosed is a novel MESFET having a gate (50) which is of submicron length, planar and provided with submicron sidewall insulator spacers (14˝). The source (30) and drain (32) are very shallow and are self-aligned to the gate via the spacers. The device is endowed with minimal gate overlap capacitance since the gate has little lapping over the source/drain contact metal and the associated passivation dielectric. Disclosed too is a process of fabrication of the MESFET in which starting with a GaAs substrate having a shallow N- layer covered with nitride, a submicron-wide gate consisting of upper and lower portions made of dissimilar materials is formed. Multilayer organic and sidewall image transfer techniques are employed for forming the mask. The nitride is etched using the gate mask. N+ source/drain are formed by ion implantation. The lower portion of the gate mask is etched to expose the periphery of the nitride. Refractory metal for source/drain contacts is deposited. An oxide layer is deposited to passivate the source/drain contacts and to fully cover the exposed nitride periphery. The gate mask is removed. High temperature anneal is accomplished to simultaneously activate the N+ regions and anneal the contact metal. By RIE the exposed nitride removed leaving submicron spacers thereof. Gate metal is deposited in the gate region. Excess gate metal is removed to obtain a gate which has a planar top and has little lapping over the source/drain contacts.