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    CMOS integrated circuit fabrication
    1.
    发明公开
    CMOS integrated circuit fabrication 失效
    Herstellung einer CMOS-integrierten Schaltung。

    公开(公告)号：EP0660394A1

    公开(公告)日：1995-06-28

    申请号：EP94307649.7

    申请日：1994-10-19

    Applicant: AT&T Corp.

    Inventor： Lee, Kuo-Hua ,  Lin, Horng-dar ,  Yan, Ran-Hong ,  Yu, Chen-Hua Douglas

    IPC: H01L21/82 ,  H01L27/092

    CPC classification number: H01L27/0928 ,  H01L21/823842 ,  Y10S148/02

    Abstract: A semiconductor integrated circuit, and process for its manufacture, are disclosed which contains both n⁺ and p⁺ gates that do not pose a risk of dopant interdiffusion. Both n⁺ and p⁺ gates may be fabricated by conventional means. The gate structures are severed over the tub boundaries (e.g., 61). A titanium nitride interconnective layer (e.g., 31) is deposited and patterned over the gates. The interconnective layer preserves connectivity between the n⁺ and p⁺ gates without risk of deleterious dopant interdiffusion.

    Abstract translation: 公开了一种半导体集成电路及其制造方法，其包含不构成掺杂相互扩散的风险的n +和p +门。 n +和p + +门可以通过常规方法制造。 门结构在桶边界上被切断（例如，61）。 氮化钛互连层（例如31）在栅极上沉积和图案化。 互连层保留了n +和p +门之间的连通性，而没有有害的掺杂剂相互扩散的风险。

    Method of manufacturing a semiconductor device having interconnections located both above a semiconductor region and above an isolation region adjoining it
    6.
    发明公开
    Method of manufacturing a semiconductor device having interconnections located both above a semiconductor region and above an isolation region adjoining it 失效
    制造具有被安装在一个半导体区域和上述邻接的隔离区域互连的半导体器件的方法。

    公开(公告)号：EP0289089A1

    公开(公告)日：1988-11-02

    申请号：EP88200798.2

    申请日：1988-04-26

    Applicant: Philips Electronics N.V.

    Inventor： Den Blanken, Hubertus Johannes

    IPC: H01L21/768 ,  H01L23/52

    CPC classification number: H01L21/76885 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10S148/02 ,  Y10S148/105 ,  Y10S438/926 ,  H01L2924/00

    Abstract: A method of manufacturing a semiconductor device, in which a first pattern of conductors (20), an isolating layer (21) and a second pattern of conductors (22) are successively provided on a surface (2) of a semiconductor body (1) adjoined by a number of isolation regions (4, 10) and a number of semiconductor regions (3). Mutual contacts are established between the two patterns (20, 22) and these contacts are located both above a semiconductor region (3) and above an adjoining isolation region (4, 10) by forming conductive pillars (44) in the first pattern (20), exposing a tip (51) of the pillars (44) after an isolating layer (50) has been provided and providing the second pattern (22) over the tip (51) of the pillars (44). Thus, a large amount is saved on the surface (2).

    Abstract translation: 一种制造半导体器件，在其上连续地设置的表面上的导体（20），以隔离层（21）和导体的第二图案（22）的第一图案的方法（2）的半导体主体（1）的 由多个隔离区域的（4，10）和多个半导体区域（3）邻接。 相互接触通过形成在第一图案导电柱（44）的两个模式之间建立（20，22）和合成触点位于两者的半导体区域上述（3）和上述在邻接的隔离区域（4，10）（20 ），在隔离层（50）已经被提供并且提供在柱（44）的尖端（51）的第二图案（22）之后暴露所述支柱（44）的尖端（51）。 因此，大量的被保存的表面（2）上。

    Method of producing a semiconductor device comprising a selective vapour growth technique
    8.
    发明公开
    Method of producing a semiconductor device comprising a selective vapour growth technique 失效
    一种用于通过选择性气相结垢技术生产半导体器件的工艺。

    公开(公告)号：EP0147913A2

    公开(公告)日：1985-07-10

    申请号：EP84305652.4

    申请日：1984-08-20

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Moriya, Takahiko c/o Patent Division ,  Nakada, Saburo c/o Patent Division

    IPC: H01L21/28 ,  H01L21/60

    CPC classification number: H01L29/41775 ,  H01L21/28 ,  H01L21/28562 ,  H01L21/76879 ,  Y10S148/019 ,  Y10S148/02 ,  Y10S148/026

    Abstract: Disclosed is a method of producing a semiconductor device, comprising the steps of introducing an impurity of one conductivity type into a semiconductor substrate (21) of an opposite conductivity type having an insulating film pattern (22) formed on a surface thereof, using the insulating film pattern (22) as a mask to form a diffusion layer (25a, 25b); and forming a metal film (27a to 27c) on the diffusion layer (25a, 25b) by selective vapor growth with a mixture of a metal source gas and an additive gas used as a feed gas, said vapor growth being carried out such that the distance of entry of the metal film (27a, 27b) from the edge of the insulating film pattern (22) to the interface between the insulating film pattern (22) and the diffusion layer (25a, 25b) is smaller than the depth of the pn junction of the diffusion layer (25a, 25b). The particular method makes it possible to achieve a selective vapor growth of a metal film on the diffusion layer without deteriorating the pn junction characteristics.

    Abstract translation: 本发明公开了生产半导体器件的方法，包括在一导电型的杂质引入到具有在绝缘膜图案（22）而形成在其表面上的相反导电类型的半导体衬底（21）的步骤，用绝缘的方法 膜图案（22）作为掩模，以形成扩散层（25A，25B）; 和形成扩散层上形成金属薄膜 - （27a至27c中）（25A，25B）通过用金属源气体的混合物选择性气相生长并与添加剂用作进料气体的气体，所述蒸气生长正在开展寻求DASS模 金属电影的条目的距离（27A，27B）从所述绝缘膜图案（22），以在绝缘膜图案（22）和所述扩散层之间的界面的边缘（25A，25B）比的深度小 扩散层的pn结（25A，25B）。 的具体方法，能够实现的金属膜 - 上的扩散层的选择性气相生长而不恶化pn结特性。

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