摘要:
Disclosed is a novel MESFET having a gate (50) which is of submicron length, planar and provided with submicron sidewall insulator spacers (14˝). The source (30) and drain (32) are very shallow and are self-aligned to the gate via the spacers. The device is endowed with minimal gate overlap capacitance since the gate has little lapping over the source/drain contact metal and the associated passivation dielectric. Disclosed too is a process of fabrication of the MESFET in which starting with a GaAs substrate having a shallow N- layer covered with nitride, a submicron-wide gate consisting of upper and lower portions made of dissimilar materials is formed. Multilayer organic and sidewall image transfer techniques are employed for forming the mask. The nitride is etched using the gate mask. N+ source/drain are formed by ion implantation. The lower portion of the gate mask is etched to expose the periphery of the nitride. Refractory metal for source/drain contacts is deposited. An oxide layer is deposited to passivate the source/drain contacts and to fully cover the exposed nitride periphery. The gate mask is removed. High temperature anneal is accomplished to simultaneously activate the N+ regions and anneal the contact metal. By RIE the exposed nitride removed leaving submicron spacers thereof. Gate metal is deposited in the gate region. Excess gate metal is removed to obtain a gate which has a planar top and has little lapping over the source/drain contacts.
摘要:
A Conductor Insulator Semiconductor (CIS) heterojunction transistor is described hereunder. The CIS transistor is on a semi-insulating or insulating substrate (102). A layer (104) of n type Si is deposited on the substrate. A trench (106) is formed through the n type Si layer, and may extend slightly into the substrate. The trench is filled with an insulator, preferably SiO₂. A layer (112) of p type Si 1-z Ge z (where z is the mole fraction of Ge and 0.1 ≦ z ≦ 0.9) is deposited on the n type Si layer. A p⁺ base contact region (114) is defined in the p type Si 1-z Ge z region above the oxide filled trench. A n type dopant is ion implanted into both the Si 1-z Ge z and n Si layers and may extend slightly into the substrate, forming a collector region (120). A thin oxide layer (136) is deposited on the Si 1-z Ge z layer and a low work function metal such as Al, Mg, Mn, or Ti is selectively deposited on the thin oxide and to define an emitter (130). Alternatively, the emitter may be p⁺ polysilicon. Next, the thin oxide is opened to define collector (134) and base (132) contacts. A suitable metal, such as Al is deposited in the base and collector contacts.
摘要:
Disclosed is a process for forming a high-speed, self-aligned GaAs-gate field effect transistor with submicron channel length. Starting with a semi insulating GaAs substrate (10) having a thin gate insulator layer of undoped AlGaAs (12) and a comparatively thick highly doped GaAs layer (40), a metal (32) contacting the doped GaAs layer is controllably formed by sidewall image transfer and planarization etchback technique. The thickness and width of the metal strip are in the low submicron range. Using the metal strip as a mask, the doped GaAs is patterned into a GaAs gate for the FET having the characteristics of submicron width (i.e., the dimension of the gate measured along the source drain), substantially vertical walls and contacted on the top thereof in a self-aligned relationship by the metal strip. Next, a submicron wide insulator sidewall (48) is formed on the vertical walls of the gate. By ion implantation across the AlGaAs layer using the gate structure and a patterned photoresist as a mask, source (52) and drain (54) are formed in the substrate in self-aligned relation with the gate. Contact metallization is formed to electrically contact the source, drain and the gate.
摘要:
A Conductor Insulator Semiconductor (CIS) heterojunction transistor is described hereunder. The CIS transistor is on a semi-insulating or insulating substrate (102). A layer (104) of n type Si is deposited on the substrate. A trench (106) is formed through the n type Si layer, and may extend slightly into the substrate. The trench is filled with an insulator, preferably SiO₂. A layer (112) of p type Si 1-z Ge z (where z is the mole fraction of Ge and 0.1 ≦ z ≦ 0.9) is deposited on the n type Si layer. A p⁺ base contact region (114) is defined in the p type Si 1-z Ge z region above the oxide filled trench. A n type dopant is ion implanted into both the Si 1-z Ge z and n Si layers and may extend slightly into the substrate, forming a collector region (120). A thin oxide layer (136) is deposited on the Si 1-z Ge z layer and a low work function metal such as Al, Mg, Mn, or Ti is selectively deposited on the thin oxide and to define an emitter (130). Alternatively, the emitter may be p⁺ polysilicon. Next, the thin oxide is opened to define collector (134) and base (132) contacts. A suitable metal, such as Al is deposited in the base and collector contacts.
摘要:
A superheterojunction Field Effect Transistor (FET) with a multi-region channel on a Silicon (Si) substrate (204). The FET is a Metal Semiconductor FET (MESFET) or, alternatively, a Junction FET (JFET). The multi-region channel has : a first region (250) of Si extending from the FET's source to a point under the FET's gate, beyond the gate's midpoint ; a second region extending from the first region to the FET's drain (240), comprised of a superlattice of alternating Si and SiGe layers (206) ; and, a third region (202) of Si extending under the first two regions from the source to the drain. The first region has a laterally graded dopant that creates an accelerating electric field. The superlattice structure increases electron mobility and transit velocity.
摘要:
A superheterojunction Field Effect Transistor (FET) with a multi-region channel on a Silicon (Si) substrate (204). The FET is a Metal Semiconductor FET (MESFET) or, alternatively, a Junction FET (JFET). The multi-region channel has : a first region (250) of Si extending from the FET's source to a point under the FET's gate, beyond the gate's midpoint ; a second region extending from the first region to the FET's drain (240), comprised of a superlattice of alternating Si and SiGe layers (206) ; and, a third region (202) of Si extending under the first two regions from the source to the drain. The first region has a laterally graded dopant that creates an accelerating electric field. The superlattice structure increases electron mobility and transit velocity.