High speed GaAs mesfet having refractory contacts and a self-aligned cold gate fabrication process
    1.
    发明公开
    High speed GaAs mesfet having refractory contacts and a self-aligned cold gate fabrication process 失效
    高速的GaAs MESFET与用于自对准栅极冷耐高温材料和制造工艺的触点。

    公开(公告)号:EP0287769A1

    公开(公告)日:1988-10-26

    申请号:EP88102435.0

    申请日:1988-02-19

    IPC分类号: H01L29/64 H01L21/28 H01L21/00

    摘要: Disclosed is a novel MESFET having a gate (50) which is of submicron length, planar and provided with submicron sidewall insulator spacers (14˝). The source (30) and drain (32) are very shallow and are self-aligned to the gate via the spacers. The device is endowed with minimal gate overlap capacitance since the gate has little lapping over the source/drain contact metal and the associated passivation dielectric. Disclosed too is a process of fabrication of the MESFET in which starting with a GaAs substrate having a shallow N- layer covered with nitride, a submicron-wide gate consisting of upper and lower portions made of dissimilar materials is formed. Multilayer organic and sidewall image transfer techniques are employed for forming the mask. The nitride is etched using the gate mask. N+ source/drain are formed by ion implantation. The lower portion of the gate mask is etched to expose the periphery of the nitride. Refractory metal for source/drain contacts is deposited. An oxide layer is deposited to passivate the source/drain contacts and to fully cover the exposed nitride periphery. The gate mask is removed. High temperature anneal is accomplished to simultaneously activate the N+ regions and anneal the contact metal. By RIE the exposed nitride removed leaving submicron spacers thereof. Gate metal is deposited in the gate region. Excess gate metal is removed to obtain a gate which has a planar top and has little lapping over the source/drain contacts.

    摘要翻译: 本发明公开了具有门(50),所有这些是亚微米的长度,平面的和提供具有亚微米侧壁绝缘子隔板(14秒)的新颖MESFET。 源(30)和漏极(32)是非常浅的和自对准经由间隔物栅极。 该设备被赋予了最小的栅重叠电容,因为栅极具有比源极/漏极接触金属和相关联的电介质钝化小研磨。 还公开了在其中从具有覆盖有氮化物的浅N层的GaAs衬底中,亚微米范围内的栅极由......组成制成异种材料的上部和下部的是形成在所述MESFET的制造的方法。 多层结构的有机和侧壁图像转移技术被用于形成掩模。的氮化物是使用栅极掩模。N +源极/漏极通过离子注入形成刻蚀。 所述栅极掩模的下部被蚀刻以暴露所述氮化物的周边。 用于源极/漏极接触的难熔金属淀积。 氧化物层沉积到钝化源/漏接触,并完全覆盖暴露的氮化物周边。 栅极掩模被去除。 高温退火是造诣的同时激活N +区域和退火金属接触。 通过RIE除去,留下它们的亚微米的暴露的氮化物间隔物。 栅极金属在栅极区域沉积。 过量金属栅极被去除,得到栅极其中有一个平坦的顶和具有在所述源极/漏极接触小研磨。

    Conductor-insulator-semiconductor (CIS) transistor
    2.
    发明公开
    Conductor-insulator-semiconductor (CIS) transistor 失效
    导体 - 绝缘层 - 半导体(CIS)晶体管。

    公开(公告)号:EP0660418A3

    公开(公告)日:1995-08-30

    申请号:EP94480122.4

    申请日:1994-11-08

    IPC分类号: H01L29/72 H01L21/331

    摘要: A Conductor Insulator Semiconductor (CIS) heterojunction transistor is described hereunder. The CIS transistor is on a semi-insulating or insulating substrate (102). A layer (104) of n type Si is deposited on the substrate. A trench (106) is formed through the n type Si layer, and may extend slightly into the substrate. The trench is filled with an insulator, preferably SiO₂. A layer (112) of p type Si 1-z Ge z (where z is the mole fraction of Ge and 0.1 ≦ z ≦ 0.9) is deposited on the n type Si layer. A p⁺ base contact region (114) is defined in the p type Si 1-z Ge z region above the oxide filled trench. A n type dopant is ion implanted into both the Si 1-z Ge z and n Si layers and may extend slightly into the substrate, forming a collector region (120). A thin oxide layer (136) is deposited on the Si 1-z Ge z layer and a low work function metal such as Al, Mg, Mn, or Ti is selectively deposited on the thin oxide and to define an emitter (130). Alternatively, the emitter may be p⁺ polysilicon. Next, the thin oxide is opened to define collector (134) and base (132) contacts. A suitable metal, such as Al is deposited in the base and collector contacts.

    Fabrication of insulated gallium arsenide-gate FET with self-aligned source/drain and submicron channel length
    3.
    发明公开
    Fabrication of insulated gallium arsenide-gate FET with self-aligned source/drain and submicron channel length 失效
    来源/排水和Submikron-Kanalzone的Herstellung von isolierendem Gallium-Arsenid-Gate-Fet mit Selbstjustierten。

    公开(公告)号:EP0240683A1

    公开(公告)日:1987-10-14

    申请号:EP87102621.7

    申请日:1987-02-24

    IPC分类号: H01L21/28

    CPC分类号: H01L29/66924

    摘要: Disclosed is a process for forming a high-speed, self-aligned GaAs-gate field effect transistor with submicron channel length. Starting with a semi insulating GaAs substrate (10) having a thin gate insulator layer of undoped AlGaAs (12) and a comparatively thick highly doped GaAs layer (40), a metal (32) contacting the doped GaAs layer is controllably formed by sidewall image transfer and planarization etchback technique. The thickness and width of the metal strip are in the low submicron range. Using the metal strip as a mask, the doped GaAs is patterned into a GaAs gate for the FET having the characteristics of submicron width (i.e., the dimension of the gate measured along the source drain), substantially vertical walls and contacted on the top thereof in a self-aligned relationship by the metal strip. Next, a submicron wide insulator sidewall (48) is formed on the vertical walls of the gate. By ion implantation across the AlGaAs layer using the gate structure and a patterned photoresist as a mask, source (52) and drain (54) are formed in the substrate in self-aligned relation with the gate. Contact metallization is formed to electrically contact the source, drain and the gate.

    摘要翻译: 公开了一种形成具有亚微米通道长度的高速,自对准GaAs栅极场效应晶体管的工艺。 从半绝缘GaAs衬底(10)开始,具有非掺杂AlGaAs(12)的薄栅极绝缘体层和相当厚的高掺杂GaAs层(40),与掺杂GaAs层接触的金属(32)可由侧壁图像 转移和平面化回蚀技术。 金属带的厚度和宽度处于亚微米范围内。 使用金属带作为掩模,将掺杂的GaAs图案化为具有亚微米宽度特性(即沿源极漏极测量的栅极的尺寸)的FET的GaAs栅极,基本垂直的壁并在其顶部接触 以金属条的自对准关系。 接下来,在门的垂直壁上形成亚微米宽的绝缘体侧壁(48)。 通过使用栅极结构和图案化的光致抗蚀剂作为掩模在AlGaAs层上的离子注入,源(52)和漏极(54)以与栅极自对准的关系形成在衬底中。 接触金属化形成为电接触源极,漏极和栅极。

    Conductor-insulator-semiconductor (CIS) transistor
    4.
    发明公开
    Conductor-insulator-semiconductor (CIS) transistor 失效
    Leiter-Insulator-Halbleiter(CIS)晶体管。

    公开(公告)号:EP0660418A2

    公开(公告)日:1995-06-28

    申请号:EP94480122.4

    申请日:1994-11-08

    IPC分类号: H01L29/72 H01L21/331

    摘要: A Conductor Insulator Semiconductor (CIS) heterojunction transistor is described hereunder. The CIS transistor is on a semi-insulating or insulating substrate (102). A layer (104) of n type Si is deposited on the substrate. A trench (106) is formed through the n type Si layer, and may extend slightly into the substrate. The trench is filled with an insulator, preferably SiO₂. A layer (112) of p type Si 1-z Ge z (where z is the mole fraction of Ge and 0.1 ≦ z ≦ 0.9) is deposited on the n type Si layer. A p⁺ base contact region (114) is defined in the p type Si 1-z Ge z region above the oxide filled trench. A n type dopant is ion implanted into both the Si 1-z Ge z and n Si layers and may extend slightly into the substrate, forming a collector region (120). A thin oxide layer (136) is deposited on the Si 1-z Ge z layer and a low work function metal such as Al, Mg, Mn, or Ti is selectively deposited on the thin oxide and to define an emitter (130). Alternatively, the emitter may be p⁺ polysilicon. Next, the thin oxide is opened to define collector (134) and base (132) contacts. A suitable metal, such as Al is deposited in the base and collector contacts.

    摘要翻译: 导体绝缘体半导体(CIS)晶体管包括衬底,在衬底层上的第一半导体材料的第一导电层和第一导电层上的第二半导体材料的第二导电层。 薄绝缘垫位于第二导电层上,第一电极位于薄绝缘垫上。 第二电极和第三电极设置在第二导电层上。 第二导电层包括第一导电类型的区域和第二导电类型的区域,第二导电类型区域从第三电极向下延伸穿过第二导电层。 CIS晶体管还包括在第一导电层中的沟槽,沟槽被绝缘材料填充。

    High performance MESFET with multiple quantum wells
    6.
    发明公开
    High performance MESFET with multiple quantum wells 失效
    Hochleistungs-MESFET mit mehrfachen Quantum-Wells。

    公开(公告)号:EP0607729A2

    公开(公告)日:1994-07-27

    申请号:EP93480207.5

    申请日:1993-12-03

    摘要: A superheterojunction Field Effect Transistor (FET) with a multi-region channel on a Silicon (Si) substrate (204). The FET is a Metal Semiconductor FET (MESFET) or, alternatively, a Junction FET (JFET). The multi-region channel has : a first region (250) of Si extending from the FET's source to a point under the FET's gate, beyond the gate's midpoint ; a second region extending from the first region to the FET's drain (240), comprised of a superlattice of alternating Si and SiGe layers (206) ; and, a third region (202) of Si extending under the first two regions from the source to the drain. The first region has a laterally graded dopant that creates an accelerating electric field. The superlattice structure increases electron mobility and transit velocity.

    摘要翻译: 在硅(Si)衬底(204)上具有多区域沟道的超导体场效应晶体管(FET)。 FET是金属半导体FET(MESFET),或者是结型FET(JFET)。 多区域通道具有:从FET源极延伸到FET栅极下方的点的第一区域(250),超过栅极的中点; 从所述第一区域延伸到所述FET的漏极(240)的第二区域,包括交替的Si和SiGe层(206)的超晶格; 以及在从源极到漏极的前两个区域下延伸的Si的第三区域(202)。 第一区域具有产生加速电场的横向渐变掺杂剂。 超晶格结构增加电子迁移率和转运速度。