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1.发明授权Circuits for accessing a variable width data bus with a variable width data field 失效用于访问具有可变宽度数据字段的可变宽度数据总线的电路
公开(公告)号：EP0097834B1
公开(公告)日：1989-09-13
申请号：EP83105439.0
申请日：1983-06-01
CPC分类号： G06F7/764 , G06F5/00 , G06F5/01 , G06F13/4018
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公开(公告)号：EP0127007A3
公开(公告)日：1987-05-20
申请号：EP84104923
申请日：1984-05-03
IPC分类号： G06F03/04
CPC分类号： G06F13/4018
摘要： Input data words of variable data field width are interfaced to a fixed width data bus. The apparatus includes a circuit incorporating a modulo N c down shifter for translating an N f bit length input data word into an N c bit length output data word for interfacing with an N c bit length data bus and further including mask means for generating a mask when the N f bit length is not an even multiple of the N c bit length.
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公开(公告)号：EP0171518B1
公开(公告)日：1992-04-29
申请号：EP85105724.0
申请日：1985-05-10
IPC分类号： G11C7/00 , G11C11/409
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1075 , G11C11/4093
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公开(公告)号：EP0031488A3
公开(公告)日：1981-07-15
申请号：EP80107613
申请日：1980-12-04
CPC分类号： G11C8/16 , G11C11/4113
摘要： A random access memory system is disclosed in which data stored in two distinct memory locations defined by distinct address signals can be non-destructively read out simultaneously. The system employs a matrix of two-port memory cells (21), each cell functioning to store one binary bit of data in a conventional cross-coupled common emitter flip-flop. A pair of input/output transistors (T z , T 3 ) have their emitters connected to the respective control nodes (A, B) of the static cell, their bases connected to first (WLO) and second word lines (WL1), and their collectors connected to first (BSO) and second (BS1) bit sense lines. The word lines and bit lines are addressed and pulsed such that during reading of the selected cells, current flows through only one of the input transistors of one of the cells to a sense line whereon, during writing, current flows through both of the input/output transistors, the direction of current flow during writing depending on the value of the binary bit being stored. The input/output transistors associated with each cell are integrated onto the chip and occupy only slightly more area than multi-configured devices conventionally employed in prior art two-port cells.
摘要翻译： 公开了一种随机存取存储器系统，其中存储在由不同地址信号定义的两个不同存储器位置中的数据可以被非破坏性地同时读出。 该系统采用双端口存储器单元的矩阵，每个单元用于在传统的交叉耦合公共发射极触发器中存储一个二进制数据位。 一对输入/输出晶体管的发射器连接到静态单元的相应控制节点，它们的基极连接到第一和第二字线，并且它们的集电极连接到第一和第二位感测线。 字线和位线被寻址和脉冲，使得在读取所选择的单元期间，电流仅流过感测线的单元之一的输入晶体管中的一个，在写入期间，电流流过输入/ 输出晶体管，写入期间电流的方向取决于存储的二进制位的值。 与每个单元相关联的输入/输出晶体管被集成到芯片上并且仅比现有技术的双端口单元中常规使用的多配置器件占据稍微更多的面积。
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5.发明公开Memory cell and its use in a random access matrix memory system 失效Speicherzelle und ihre Verwendung in einem Direktzugriffspeichermatrixsystem。
公开(公告)号：EP0031488A2
公开(公告)日：1981-07-08
申请号：EP80107613.4
申请日：1980-12-04
CPC分类号： G11C8/16 , G11C11/4113
摘要： A random access memory system is disclosed in which data stored in two distinct memory locations defined by distinct address signals can be non-destructively read out simultaneously. The system employs a matrix of two-port memory cells (21), each cell functioning to store one binary bit of data in a conventional cross-coupled common emitter flip-flop. A pair of input/output transistors (T z , T 3 ) have their emitters connected to the respective control nodes (A, B) of the static cell, their bases connected to first (WLO) and second word lines (WL1), and their collectors connected to first (BSO) and second (BS1) bit sense lines. The word lines and bit lines are addressed and pulsed such that during reading of the selected cells, current flows through only one of the input transistors of one of the cells to a sense line whereon, during writing, current flows through both of the input/output transistors, the direction of current flow during writing depending on the value of the binary bit being stored. The input/output transistors associated with each cell are integrated onto the chip and occupy only slightly more area than multi-configured devices conventionally employed in prior art two-port cells.
摘要翻译： 公开了一种随机存取存储器系统，其中存储在由不同地址信号定义的两个不同存储器位置中的数据可以被非破坏性地同时读出。 该系统采用双端口存储器单元的矩阵，每个单元用于在传统的交叉耦合公共发射极触发器中存储一个二进制数据位。 一对输入/输出晶体管的发射器连接到静态单元的相应控制节点，它们的基极连接到第一和第二字线，并且它们的集电极连接到第一和第二位感测线。 字线和位线被寻址和脉冲，使得在读取所选择的单元期间，电流仅流过感测线的单元之一的输入晶体管中的一个，在写入期间，电流流过输入/ 输出晶体管，写入期间电流的方向取决于存储的二进制位的值。 与每个单元相关联的输入/输出晶体管被集成到芯片上并且仅比现有技术的双端口单元中常规使用的多配置器件占据稍微更多的面积。
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公开(公告)号：EP0330007A3
公开(公告)日：1991-09-04
申请号：EP89102060.4
申请日：1989-02-07
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F12/0859 , G06F12/0864
摘要： An on-chip VLSI cache architecture including a single-port, late-select, cache array organized as an n-way set-associative cache (having n congruence classes) including a plurality of functionally integrated units on-chip in addition to the cache array and including a normal read/write central processing unit (CPU) access function which provides an architectural organization for allowing the chip to be used in 1) a fast, "late-select" operation which may be provided with any desired degree of set-associativity while achieving an effective one-cycle write operation, and 2) a cache reload function which provides a highly parallel store-back and reload operation to substantially reduce the reload time, particularly for a store-in cache organization. The cache chip organization and architecture provide a late-select cache having a nearly transparent, multiple word reload by incorporating a Cache-Reload Buffer (CRB), a store-back buffer and a load-through function all included on the cache array chip for reloading, and a delayed write-enable for achieving an effective one-cycle write operation. Two separate decoder functions are integrated on the chip, one for cache access for normal read/write operations to and from the central processing unit (CPU) and one for cache reload which also provides interim access to data which has been transferred out of main memory to the chip but not yet reloaded into the cache array. These two decoders provide for different accessing modes as required of the central processing unit (CPU) or main memory operations.
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7.发明公开
公开(公告)号：EP0126976A3
公开(公告)日：1987-10-07
申请号：EP84104624
申请日：1984-04-25
IPC分类号： G06F15/16
CPC分类号： G06F15/167 , G06F12/0813
摘要： A communicating random access shared memory configuration for a multiprocessor system is connected to the processors for transferring data between the processors. The random access memory configuration includes a plurality of interconnected random access memory chips, each of these memory chips including first and second separate memory bit arrays having N word storage locations of M bit length with M bit buffer means connected in between the first and second bit arrays of each memory chip, and first and second input/output ports connected to first and second bit arrays on each chip for entering and removing data externally to and from the chip. A control means is located on each chip and connected to the first and second memory arrays and the M bit buffer means for transferring data between the first and second memory arrays and into and out of the first and second input/output ports.
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公开(公告)号：EP0171518A2
公开(公告)日：1986-02-19
申请号：EP85105724.0
申请日：1985-05-10
IPC分类号： G11C7/00 , G11C11/409
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1075 , G11C11/4093
摘要： A dynamic row buffer circuit is disclosed for a dynamic random access memory (DRAM) chip which enables the DRAM chip to be used for special function applications. The dynamic row buffer comprises a row buffer master register and a row buffer slave register. The row buffer master register comprises a plurality of master circuits (M1) and a plurality of slave circuits (S1). Likewise, the row buffer slave register comprises a plurality of master circuits (M2) and a plurality of slave circuits (S2). The row buffer master register is parallel load and parallel read-out with the outputs of the master register slave circuits being connected to the master circuits of the slave register. The row buffer slave register is a parallel load, serial read-out register with the output being shifted out of a secondary output port. The entire row buffer can be isolated from the memory array, and when so isolated, the memory array can be accessed through the primary input/output port in the same way as in an ordinary DRAM chip. This arrangement permits the conversion of a DRAM chip to a dual port display, of which a specific example is disclosed, or some other special function RAM thereby adding a large value to the DRAM chip with little additional cost.
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公开(公告)号：EP0127007B1
公开(公告)日：1989-08-16
申请号：EP84104923.2
申请日：1984-05-03
IPC分类号： G06F13/40
CPC分类号： G06F13/4018
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公开(公告)号：EP0171518A3
公开(公告)日：1988-08-03
申请号：EP85105724
申请日：1985-05-10
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1075 , G11C11/4093
摘要： A dynamic row buffer circuit is disclosed for a dynamic random access memory (DRAM) chip which enables the DRAM chip to be used for special function applications. The dynamic row buffer comprises a row buffer master register and a row buffer slave register. The row buffer master register comprises a plurality of master circuits (M1) and a plurality of slave circuits (S1). Likewise, the row buffer slave register comprises a plurality of master circuits (M2) and a plurality of slave circuits (S2). The row buffer master register is parallel load and parallel read-out with the outputs of the master register slave circuits being connected to the master circuits of the slave register. The row buffer slave register is a parallel load, serial read-out register with the output being shifted out of a secondary output port. The entire row buffer can be isolated from the memory array, and when so isolated, the memory array can be accessed through the primary input/output port in the same way as in an ordinary DRAM chip. This arrangement permits the conversion of a DRAM chip to a dual port display, of which a specific example is disclosed, or some other special function RAM thereby adding a large value to the DRAM chip with little additional cost.
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