公开(公告)号：EP2130132A1

公开(公告)日：2009-12-09

申请号：EP08726448.7

申请日：2008-03-05

申请人： Analog Devices, Inc.

发明人： WILSON, James ,  KABLOTSKY, Joshua ,  STEIN, Yosef

IPC分类号： G06F15/00

CPC分类号： G06F5/10 ,  G06F5/00 ,  G06F5/065 ,  G06F5/14 ,  G06F9/30018 ,  G06F9/3824 ,  G06F2205/126

摘要： A compute unit with an internal bit FIFO circuit includes at least one data register, a lookup table, a configuration register including FIFO base address, length and read/write mode fields for configuring a portion of the lookup table as a bit FIFO circuit and a read/write pointer register responsive to an instruction having a lookup table identification field, length of bits field and register extract/deposit field for selectively transferring in a single cycle between the FIFO circuit and the data register a bit field of specified length.

公开(公告)号：EP1416639A1

公开(公告)日：2004-05-06

申请号：EP03013828.3

申请日：2003-06-18

申请人： Agilent Technologies Inc

发明人： Poulton, Kenneth D. ,  Kopley, Thomas E. ,  Robert M. R. Neff

IPC分类号： H03M1/12 ,  G11C7/16

CPC分类号： G11C7/16 ,  G06F5/00 ,  H03M1/1215 ,  H03M1/127

摘要： The analog-to-digital conversion system (100) comprises an analog-to-digital converter (102) that includes a digital output (122), memory (106) having a data input (130) and a data output (132), an output port (110), an input data bus (104) that extends from the digital output of the analog-to-digital converter to the data input of the memory and an output data bus (108) that extends from the data output of the memory to the output port. The analog-to-digital converter is structured to generate digital samples at a sampling rate. The input data bus is structured to operate at the sampling rate of the ADC. At least one of the data output (132) of the memory, the output data bus (108) and the output port (108) is structured to operate at a maximum rate less than the sampling rate.

公开(公告)号：EP1367483A2

公开(公告)日：2003-12-03

申请号：EP03253301.0

申请日：2003-05-27

申请人： Broadcom Corporation

发明人： Wilson, Sophie

IPC分类号： G06F9/30

CPC分类号： G06F9/30014 ,  G06F5/00 ,  G06F9/30025 ,  G06F9/30036

摘要： A method of and device for performing a data expansion operation on a plurality of input data objects to generate expanded output data objects is disclosed. The method comprises receiving and decoding a data manipulation instruction defining a data expansion operation, a portion of the data manipulation instruction indicating an expansion operation from a number of predetermined types of data manipulation operations. The method includes generating one or more expansion objects responsive to the indication of an expansion operation, said expansion objects being for use in extending an input data object. The input data objects and said expansion objects are manipulated according to control information programmed to produce a set of expanded output data objects.

摘要翻译： 公开了一种用于对多个输入数据对象执行数据扩展操作以产生扩展的输出数据对象的方法和装置。 该方法包括接收和解码定义数据扩展操作的数据操作指令，数据操作指令的一部分指示来自多种预定类型的数据操作操作的扩展操作。 该方法包括响应于扩展操作的指示而生成一个或多个扩展对象，所述扩展对象用于扩展输入数据对象。 根据编程为产生一组扩展输出数据对象的控制信息来操纵输入数据对象和所述扩展对象。

公开(公告)号：EP1323026A1

公开(公告)日：2003-07-02

申请号：EP01962212.5

申请日：2001-08-16

申请人： INTEL CORPORATION

发明人： GANAPATHY, Kumar ,  KANAPATHIPILLAI, Ruban

IPC分类号： G06F7/38 ,  G06F7/49 ,  G06F7/60 ,  G06F9/302 ,  G06F9/315

CPC分类号： G06F9/383 ,  G06F5/00 ,  G06F7/4806 ,  G06F7/49921 ,  G06F7/5318 ,  G06F7/5332 ,  G06F7/5443 ,  G06F7/57 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/381 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3853 ,  G06F9/3877 ,  G06F9/3885 ,  G06F17/10

摘要： An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The ISA implemented with the ASSP, is adapted to DSP algorithmic structures. The ISA of the present invention includes flexible data typing, permutation, and type matching operations (1101, 1102, 1104 and 1106). The flexible data typing, permutation and type matching of operands provides programming flexibility to support different filtering and DSP algorithms having different types of filter coefficients or data samples. A data typer and aligner within each signal processing unit within the ASSP supports flexible data typing, permutation, and type matching of operands of the instruction set architecture.

公开(公告)号：EP1080431A1

公开(公告)日：2001-03-07

申请号：EP98939466.3

申请日：1998-09-02

申请人： Acqiris

发明人： HUNGERBUEHLER, Viktor, M. ,  MAURON, Bernard

IPC分类号： G06F17/40 ,  H03M1/00

CPC分类号： G06F5/00

摘要： The invention concerns a data acquisition system comprising a circuit for converting a high frequency analog input signal (a) into a plurality of digital signals (D1-DN, R) to be processed by a digital processing system comprising at least one digital processor (8) including a digitizer (1) with m bits, a demultiplexer (2) for delivering in parallel N sampling values with m bits successively supplied by said digitizer (1), a memory (5) for storing the demultiplexed sampling values, said memory (5) being accessible by said digital processing system (8). The invention is characterised in that the circuit further comprises a digital circuit for processing (6) in real time said demultiplexed sampling values, capable of supplying processed results to said digital processing system (8). Said digitizer (1) sampling frequency is higher than said digital processor (8) working frequency.

公开(公告)号：EP0899652A3

公开(公告)日：1999-11-17

申请号：EP98114071.8

申请日：1998-07-28

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Ogawa, Noriyuki

IPC分类号： G06F5/00

CPC分类号： G06F5/00

摘要： Transmit data generated in processes in which a utilization portion 20 performs arbitrary application processing are transmitted to an exterior in accordance with a previously determined protocol in a control portion 10. A RAM 30 comprises a transmission buffer 34 and a management table 35 for managing a state where each of the transmit data, whose request for transmission has been accepted by the control portion 10, is transmitted and the location, on the transmission buffer, of the transmit data. The utilization portion 20 outputs, when the transmit data is generated, a request to acquire a data write area to the control portion 10. Correspondingly, the control portion 10 refers to the management table 35, to specify a data write area where writing is newly allowed in the transmission buffer 34 and present the specified data write area to the utilization portion 20. The utilization portion 20 writes the transmit data into the presented data write area. The RAM 30 comprises an area 51 managed by the control portion 10 and an area 9i managed by a utilization portion 2i (i = any one of 1 to N). The control portion management area 51 comprises a first receiving buffer 81, a second receiving buffer 6i and a busy flag 7i. Each of the utilization portion management area 9i comprises a data transcription area 9ia. The control portion 10 writes the received data into the first receiving buffer 81. In then transcribing the data written into the first receiving buffer 81, the control portion 11 confirms a state where the utilization portion 2i which is the destination of the data is used using the busy flag 7i. The utilization portion 2i is notified to transcribe the data onto the second receiving buffer 2i when the busy flag 7i is OFF, while transcribing the data onto the data transcription area 9ia when it is ON.

摘要翻译： 发送在其中处理产生的数据的应用部分20个执行任意的应用处理是反式mitted在外部在雅舞蹈与控制部预先确定的开采协议10.一种RAM 30包括一个传输缓冲器34和管理表35用于管理状态 其中每个传输数据，用于传输已经由控制部10接受的是谁的请求的，是发送数据的反式mitted和位置，在传输缓冲器。 应用部分20个输出，当生成的发送数据的请求来获取的数据写入区域到控制部10相对应地，控制部10参照管理表35，其中写入新是指定数据写入区 允许在传输缓冲器34和呈现指定的数据写入区域到应用部分20的利用部分20写入发送数据到所呈现的数据写入区域。 区51的RAM 30只包括由控制部10，并通过一个利用部2i（i = 1至N中的任一个）管理区域管理9i的。 控制部管理区域51包括第一接收缓冲器81，第二接收缓冲器6I和一个忙标志7I。 各个利用部管理区域9I的包括数据区的转录9ia。 控制部10接收到的数据写入到所述第一接收缓冲器81.然后转录写入到第一接收缓冲器81中的数据时，控制部11确认的状态下，利用部分2i所有这是数据的目的地使用，使用 忙标志7I。 利用部2i被通知给转录数据到第二接收缓冲器2I当忙标志7I为OFF，而转录数据到数据转录区域9ia当它是ON。

公开(公告)号：EP0547459B1

公开(公告)日：1997-03-05

申请号：EP92120808.8

申请日：1992-12-05

申请人： ALCATEL N.V.

发明人： Stephenson, William Hermas, Jr.

IPC分类号： G06F13/40

CPC分类号： G06F5/00 ,  G06F13/4018

公开(公告)号：EP0478616B1

公开(公告)日：1993-11-03

申请号：EP90909158.9

申请日：1990-06-20

申请人： PEREX LIMITED

发明人： WALKER, Barry, John 28 Mayhew Crescent

IPC分类号： G06F3/06

CPC分类号： G06F3/0601 ,  G06F5/00 ,  G06F13/4018 ,  G06F2003/0692

摘要： Apparatus for connecting an additional data storage device to a computer port, such as a printer port, that is not necessarily adapted for connection to a data storage device. An interface circuit comprises means for reading stored multibit data to a memory device and reading the multibit data from the memory device in a sequence of data segments that can be handled by a lesser number of data lines. In the case of standard parallel printer ports the data and control lines may be switched to carry respective control signals and data.

公开(公告)号：EP0559824A1

公开(公告)日：1993-09-15

申请号：EP92902795.0

申请日：1991-11-27

申请人： UNISYS CORPORATION

发明人： TEAGUE, Tommy, K.

IPC分类号： G06F13 ,  G06F5 ,  H03M7

CPC分类号： H03M7/06 ,  G06F5/00

摘要： Moyens et procédés améliorés permettant de transmettre des données binaires dans un système de communication, tel que le courrier électronique, qui restreint le nombre de caractères acceptables puvant être transmis. Dans un mode préférentiel de réalisation, les données binaires à transmettre sont d'abord soumises à une compression Welch puis sont converties en chiffre de base 85 à des fins de transmission. Du côté réception, les chiffres en base 85 reçus sont reconvertis en données binaires comprimées puis sont soumises à une décompression Welch pour obtenir les données binaires d'origine.

公开(公告)号：EP0517808A1

公开(公告)日：1992-12-16

申请号：EP91905714.0

申请日：1991-02-27

申请人： MICRO TECHNOLOGY, INC.

发明人： EIDLER, Chris, W. ,  JOHNSON, Hoke, S., III ,  SHAH, Kaushik, S.

IPC分类号： G06F13 ,  G06F3 ,  G06F5

CPC分类号： G06F5/10 ,  G06F3/0601 ,  G06F5/00 ,  G06F2003/0691

摘要： Un procédé et un appareil permettent de transférer des données de l'interface d'un dispositif à l'interface d'un autre dispositif par des éléments d'une mémoire de transfert et par un canal d'accès direct en mémoire (ADM).