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18 条记录 (耗时 0.015 秒)

    DRAM trench capacitor cell
    2.
    发明公开
    DRAM trench capacitor cell 审中-公开
    DRAM-Zelle mit Grabenkondensator

    公开(公告)号：EP1017095A3

    公开(公告)日：2005-04-13

    申请号：EP99310310.0

    申请日：1999-12-21

    申请人： Infineon Technologies AG ,  International Business Machines Corporation

    发明人： Radens, Carl ,  Gruening, Ulrike ,  DeBrosse, John ,  Mandelman, Jack

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L27/10876

    摘要： A memory cell formed in a semiconductor body includes a vertical trench (14) with a polysilicon fill (22) as a storage capacitor and a field effect transistor having a source (43) formed in the sidewall of the trench, a drain (42) formed in the semiconductor body (10) and having a surface common with a top surface of the semiconductor body, and having a channel region that includes both vertical and horizontal portions and a polysilicon gate (30) that is in an upper portion of the trench. A process for fabrication provides an insulating oxide layer (24A) at the top of the polysilicon fill portion (22) that serves as the storage node and a dielectric layer (28) that was formed as part of the gate dielectric of the transistor.

    摘要翻译： 形成在半导体本体中的存储单元包括具有作为存储电容器的多晶硅填充物（22）的垂直沟槽（14）和形成在沟槽的侧壁中的源极（43）的场效应晶体管，漏极（42） 形成在所述半导体本体（10）中并且具有与所述半导体主体的顶表面共同的表面，并且具有包括垂直和水平部分的沟道区域和位于所述沟槽的上部的多晶硅栅极（30） 。 一种制造工艺在多晶硅填充部分（22）的顶部提供用作存储节点的绝缘氧化物层（24A）和形成为晶体管的栅极电介质的一部分的电介质层（28）。

    Improved process for buried-strap self-aligned to deep storage trench
    3.
    发明公开
    Improved process for buried-strap self-aligned to deep storage trench 审中-公开
    埋深带自对准深埋储沟槽的改进工艺

    公开(公告)号：EP1022782A3

    公开(公告)日：2000-08-23

    申请号：EP00100875.4

    申请日：2000-01-18

    申请人： International Business Machines Corporation ,  Infineon Technologies AG

    发明人： Grüning, Ulrike ,  Mandelman, Jack ,  Radens, Carl

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10861

    摘要： A process for forming a buried strap self-aligned to a deep storage trench. Spacers are formed on walls of a recess over a filled deep trench capacitor and a substrate. A plug is formed in a region between the spacers. Photoresist is deposited over the spacers, the plug, and material surrounding the spacers of the plug. The photoresist is patterned, thereby exposing portions of the plug, the spacers, and the surrounding material. The spacers in the surrounding material not covered by the photoresist are selectively etched, leaving a remaining portion of the spacers. The substrate and the portion of the filled deep trench exposed by the spacer removal are selectively etched. An isolation region is formed in a space created by etching of the spacers, surrounding material, substrate, and filled deep trench.

    摘要翻译： 一种形成与深存储沟槽自对准的掩埋带的工艺。 在填充的深沟槽电容器和衬底上方的凹陷的壁上形成间隔物。 塞子形成在间隔物之间​​的区域中。 光致抗蚀剂沉积在间隔物，插塞和围绕插塞间隔物的材料上。 光致抗蚀剂被图案化，从而暴露插塞，间隔物和周围材料的一部分。 未被光致抗蚀剂覆盖的周围材料中的间隔物被选择性蚀刻，留下间隔物的剩余部分。 衬底和通过间隔件去除而暴露的填充深沟槽的部分被选择性地蚀刻。 隔离区域形成在通过蚀刻间隔物，周围材料，衬底和填充的深沟槽而形成的空间中。

    Improved process for buried-strap self-aligned to deep storage trench
    6.
    发明公开
    Improved process for buried-strap self-aligned to deep storage trench 审中-公开
    Verbeetes Verfahrenfürein zu einem tiefen Speichergraben selbstjustiertes，vergrabenes Band

    公开(公告)号：EP1022782A2

    公开(公告)日：2000-07-26

    申请号：EP00100875.4

    申请日：2000-01-18

    申请人： International Business Machines Corporation ,  Infineon Technologies AG

    发明人： Grüning, Ulrike ,  Mandelman, Jack ,  Radens, Carl

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10861

    摘要： A process for forming a buried strap self-aligned to a deep storage trench. Spacers are formed on walls of a recess over a filled deep trench capacitor and a substrate. A plug is formed in a region between the spacers. Photoresist is deposited over the spacers, the plug, and material surrounding the spacers of the plug. The photoresist is patterned, thereby exposing portions of the plug, the spacers, and the surrounding material. The spacers in the surrounding material not covered by the photoresist are selectively etched, leaving a remaining portion of the spacers. The substrate and the portion of the filled deep trench exposed by the spacer removal are selectively etched. An isolation region is formed in a space created by etching of the spacers, surrounding material, substrate, and filled deep trench.

    摘要翻译： 一种用于形成与深存储沟槽自对准的掩埋带的工艺。 垫片形成在填充的深沟槽电容器和衬底上的凹部的壁上。 插塞形成在间隔件之间的区域中。 光刻胶沉积在隔离物，插塞和围绕插塞间隔物的材料上。 对光致抗蚀剂进行图案化，从而暴露插头，间隔件和周围材料的部分。 不被光致抗蚀剂覆盖的周围材料中的间隔物被选择性地蚀刻，留下间隔物的剩余部分。 选择性地蚀刻衬底和通过间隔物去除而暴露的填充深沟槽的部分。 在通过蚀刻间隔物，周围的材料，衬底和填充的深沟槽而产生的空间中形成隔离区。

    Crack stop between neighbouring fuses for protection from fuse blow damage
    7.
    发明公开
    Crack stop between neighbouring fuses for protection from fuse blow damage 审中-公开
    Rissunterbrecher zwischen benachbarten Sicherungen zum Schutz gegenSchmelzsicherungsschäden

    公开(公告)号：EP1018765A2

    公开(公告)日：2000-07-12

    申请号：EP99126273.4

    申请日：1999-12-31

    申请人： International Business Machines Corporation ,  Siemens Aktiengesellschaft

    发明人： Narayan, Chandrasekhar ,  Kiewra, Edward ,  Radens, Carl ,  Brintzinger, Axel

    IPC分类号： H01L23/525

    CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A fuse structure in an integrated circuit chip is described that includes an insulated semiconductor substrate; a fuse bank integral to the insulated semiconductor substrate consisting of a plurality of parallel co-planar fuse links; and voids interspersed between each pair of the fuse links, the voids extending beyond a plane defined by the co-planar fuse links. The voids surrounding the spot to be hit by a laser beam during fuse blow operation act as a crack stop to prevent damage to adjacent circuit elements or other fuse links present. By suitably shaping and positioning the voids, a tighter pitch between fuses may be obtained.

    摘要翻译： 描述了集成电路芯片中的熔丝结构，其包括绝缘半导体衬底; 一个与多个并联的共面熔断体组成的绝缘半导体衬底一体的保险丝库; 以及散布在每对熔丝链之间的空隙，空隙延伸超过由共面熔丝链限定的平面。 在保险丝熔断操作期间，被激光束击中的点周围的空隙用作裂纹停止部分，以防止损坏相邻的电路元件或存在的其它熔断体。 通过适当地定形和定位空隙，可以获得保险丝之间的更紧密的间距。

    Field-shield-trench isolation for trench capacitor DRAM
    9.
    发明公开
    Field-shield-trench isolation for trench capacitor DRAM 审中-公开
    Feldplatten-GrabenisolationfürGrabenkondensator-DRAM

    公开(公告)号：EP1026745A2

    公开(公告)日：2000-08-09

    申请号：EP00101131.1

    申请日：2000-01-21

    申请人： Infineon Technologies North America Corp. ,  International Business Machines Corporation

    发明人： Mandelman, Jack A. ,  Larosa, Giuseppe ,  Radens, Carl ,  Divakaruni, Rama ,  Gruening, Ulrike

    IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L21/765

    CPC分类号： H01L27/10861 ,  H01L21/763 ,  H01L21/765 ,  H01L27/10829 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical electrical isolation trench and are isolated from support circuitry. The isolation trench has sidewalls and upper and lower portions, and encircles an area of the semiconductor body which contains the memory cells. This electrically isolates pairs of memory cells from each other and from the support circuitry contained within the semiconductor body but not located within the encircled area. The lower portion of the isolation trench is filled with an electrically conductive material that has sidewall portions thereof which are at least partly separated from the sidewalls of the lower portion of the trench by a first electrical insulator, and that has a lower portion that is in electrical contact with the semiconductor body. The upper portion of the isolation trench is filled with a second electrical insulator.

    摘要翻译： 形成在半导体主体中的动态随机存取存储器（DRAM）具有单独的存储单元对，其具有通过垂直电隔离沟槽（20）彼此隔离并且与支持电路隔离的深存储沟槽（12）。 隔离沟槽（20）具有侧壁和上部和下部，并且包围包含存储单元的半导体主体的区域。 这将存储器单元对彼此隔离并且与包含在半导体本体内但不位于环绕区域内的支撑电路电隔离。 隔离沟槽的下部填充有导电材料，该导电材料具有其侧壁部分（22），它们通过第一电绝缘体（21）至少部分地与沟槽的下部的侧壁分开，并且具有 与半导体本体电接触的下部（26）。 隔离沟槽的上部填充有第二电绝缘体（28）。