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18 条记录 (耗时 0.013 秒)

    Crack stop between neighbouring fuses for protection from fuse blow damage
    1.
    发明公开
    Crack stop between neighbouring fuses for protection from fuse blow damage 审中-公开
    Rissunterbrecher zwischen benachbarten Sicherungen zum Schutz gegenSchmelzsicherungsschäden

    公开(公告)号：EP1018765A2

    公开(公告)日：2000-07-12

    申请号：EP99126273.4

    申请日：1999-12-31

    申请人： International Business Machines Corporation ,  Siemens Aktiengesellschaft

    发明人： Narayan, Chandrasekhar ,  Kiewra, Edward ,  Radens, Carl ,  Brintzinger, Axel

    IPC分类号： H01L23/525

    CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A fuse structure in an integrated circuit chip is described that includes an insulated semiconductor substrate; a fuse bank integral to the insulated semiconductor substrate consisting of a plurality of parallel co-planar fuse links; and voids interspersed between each pair of the fuse links, the voids extending beyond a plane defined by the co-planar fuse links. The voids surrounding the spot to be hit by a laser beam during fuse blow operation act as a crack stop to prevent damage to adjacent circuit elements or other fuse links present. By suitably shaping and positioning the voids, a tighter pitch between fuses may be obtained.

    摘要翻译： 描述了集成电路芯片中的熔丝结构，其包括绝缘半导体衬底; 一个与多个并联的共面熔断体组成的绝缘半导体衬底一体的保险丝库; 以及散布在每对熔丝链之间的空隙，空隙延伸超过由共面熔丝链限定的平面。 在保险丝熔断操作期间，被激光束击中的点周围的空隙用作裂纹停止部分，以防止损坏相邻的电路元件或存在的其它熔断体。 通过适当地定形和定位空隙，可以获得保险丝之间的更紧密的间距。

    Method of forming buried strap for trench capacitor
    2.
    发明公开
    Method of forming buried strap for trench capacitor 审中-公开
    Verfahren zur Herstellung eines vergrabenen Verbindungsstreifensfüreinen Grabenkondensator

    公开(公告)号：EP0949674A2

    公开(公告)日：1999-10-13

    申请号：EP99302567.5

    申请日：1999-03-31

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Gruening, Ulrike ,  Jaiprakash, Venkatachalam C. ,  Bronner, Gary ,  Radens, Carl ,  Beintner, Jochen

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10861

    摘要： The invention relates to reducing variations in thickness and height of the buried strap of a trench capacitor. Reduced variations in thickness and height is achieved by defining the top of the buried strap by recessing the poly in the trench to the top of the buried strap. The collar is then recessed to below the top surface to define the bottom of the buried strap. A poly layer is deposited to line the sidewalls of the trench top surface of the poly trench fill, and recessed region above the collar. A etch is then used to remove the excess poly layer from the sidewalls and top surface of the poly trench fill, leaving the recessed region above the collar filled to form the buried strap. The etch removes the poly in the vertical and horizontal direction at about the same rate.

    摘要翻译： 本发明涉及减小沟槽电容器的掩埋带的厚度和高度的变化。 通过将沟槽中的多孔凹入掩埋带的顶部来限定掩埋带的顶部来实现厚度和高度的减小。 然后将套环凹入到顶部表面下方以限定掩埋带的底部。 沉积聚层以使多沟槽填充物的沟槽顶表面的侧壁和套环上方的凹陷区域对齐。 然后使用蚀刻从多沟槽填充物的侧壁和顶表面去除多余的多晶硅层，从而使填充的套环上方的凹陷区域形成掩埋带。 该蚀刻以大致相同的速率在垂直和水平方向上去除多晶。

    Buffer layer for improving control of layer thickness
    3.
    发明公开
    Buffer layer for improving control of layer thickness 有权
    缓冲层用于改善层厚控制

    公开(公告)号：EP0908938A2

    公开(公告)日：1999-04-14

    申请号：EP98307803.1

    申请日：1998-09-25

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Gruening, Ulrike ,  Beintner, Jochen ,  Radens, Carl

    IPC分类号： H01L21/31 ,  H01L21/314 ,  H01L21/033 ,  H01L21/762

    CPC分类号： H01L27/1087 ,  H01L21/3081 ,  H01L21/31 ,  H01L21/763 ,  H01L27/10867 ,  Y10S438/97

    摘要： A pad layer disposed on a semiconductor substrate 102 and a buffer layer 108 disposed within the pad layer such that the pad layer is divided into a dielectric layer 106 below the buffer layer and a mask layer 110 above the buffer layer. A method of forming layers with uniform planarity and thickness on a semiconductor chip includes the steps of providing a substrate having a thermal pad 106 formed thereon, forming a dielectric layer 106 on the thermal pad, forming a buffer layer 108 on the dielectric layer wherein the buffer layer is made from a different material than the dielectric layer and forming a mask layer 110 on the buffer layer wherein the buffer layer is made from a different material than the mask layer.

    摘要翻译： 设置在半导体衬底102上的衬垫层和设置在衬垫层内的缓冲层108，使得衬垫层被分成缓冲层下方的介电层106和缓冲层上方的掩模层110。 在半导体芯片上形成具有均匀平面性和厚度的层的方法包括以下步骤：提供其上形成有热垫106的衬底;在热垫上形成介电层106;在介电层上形成缓冲层108，其中 缓冲层由与介电层不同的材料制成并且在缓冲层上形成掩模层110，其中缓冲层由与掩模层不同的材料制成。

    DRAM trench capacitor cell
    8.
    发明公开
    DRAM trench capacitor cell 审中-公开
    DRAM-Zelle mit Grabenkondensator

    公开(公告)号：EP1017095A3

    公开(公告)日：2005-04-13

    申请号：EP99310310.0

    申请日：1999-12-21

    申请人： Infineon Technologies AG ,  International Business Machines Corporation

    发明人： Radens, Carl ,  Gruening, Ulrike ,  DeBrosse, John ,  Mandelman, Jack

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L27/10876

    摘要： A memory cell formed in a semiconductor body includes a vertical trench (14) with a polysilicon fill (22) as a storage capacitor and a field effect transistor having a source (43) formed in the sidewall of the trench, a drain (42) formed in the semiconductor body (10) and having a surface common with a top surface of the semiconductor body, and having a channel region that includes both vertical and horizontal portions and a polysilicon gate (30) that is in an upper portion of the trench. A process for fabrication provides an insulating oxide layer (24A) at the top of the polysilicon fill portion (22) that serves as the storage node and a dielectric layer (28) that was formed as part of the gate dielectric of the transistor.

    摘要翻译： 形成在半导体本体中的存储单元包括具有作为存储电容器的多晶硅填充物（22）的垂直沟槽（14）和形成在沟槽的侧壁中的源极（43）的场效应晶体管，漏极（42） 形成在所述半导体本体（10）中并且具有与所述半导体主体的顶表面共同的表面，并且具有包括垂直和水平部分的沟道区域和位于所述沟槽的上部的多晶硅栅极（30） 。 一种制造工艺在多晶硅填充部分（22）的顶部提供用作存储节点的绝缘氧化物层（24A）和形成为晶体管的栅极电介质的一部分的电介质层（28）。

    Field-shield-trench isolation for trench capacitor DRAM
    9.
    发明公开
    Field-shield-trench isolation for trench capacitor DRAM 审中-公开
    Feldplatten-GrabenisolationfürGrabenkondensator-DRAM

    公开(公告)号：EP1026745A2

    公开(公告)日：2000-08-09

    申请号：EP00101131.1

    申请日：2000-01-21

    申请人： Infineon Technologies North America Corp. ,  International Business Machines Corporation

    发明人： Mandelman, Jack A. ,  Larosa, Giuseppe ,  Radens, Carl ,  Divakaruni, Rama ,  Gruening, Ulrike

    IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L21/765

    CPC分类号： H01L27/10861 ,  H01L21/763 ,  H01L21/765 ,  H01L27/10829 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical electrical isolation trench and are isolated from support circuitry. The isolation trench has sidewalls and upper and lower portions, and encircles an area of the semiconductor body which contains the memory cells. This electrically isolates pairs of memory cells from each other and from the support circuitry contained within the semiconductor body but not located within the encircled area. The lower portion of the isolation trench is filled with an electrically conductive material that has sidewall portions thereof which are at least partly separated from the sidewalls of the lower portion of the trench by a first electrical insulator, and that has a lower portion that is in electrical contact with the semiconductor body. The upper portion of the isolation trench is filled with a second electrical insulator.

    摘要翻译： 形成在半导体主体中的动态随机存取存储器（DRAM）具有单独的存储单元对，其具有通过垂直电隔离沟槽（20）彼此隔离并且与支持电路隔离的深存储沟槽（12）。 隔离沟槽（20）具有侧壁和上部和下部，并且包围包含存储单元的半导体主体的区域。 这将存储器单元对彼此隔离并且与包含在半导体本体内但不位于环绕区域内的支撑电路电隔离。 隔离沟槽的下部填充有导电材料，该导电材料具有其侧壁部分（22），它们通过第一电绝缘体（21）至少部分地与沟槽的下部的侧壁分开，并且具有 与半导体本体电接触的下部（26）。 隔离沟槽的上部填充有第二电绝缘体（28）。