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    Process for producing transistors having independently adjustable parameters
    1.
    发明公开
    Process for producing transistors having independently adjustable parameters 审中-公开
    一种用于晶体管的与独立的可调参数的制造过程

    公开(公告)号：EP1071125A2

    公开(公告)日：2001-01-24

    申请号：EP00114376.7

    申请日：2000-07-05

    申请人： International Business Machines Corporation ,  Infineon Technologies AG

    发明人： Divakaruni, Rama ,  Gambino, Jeffrey P. ,  Mandelman, Jack ,  Rengarajan, Rajesh

    IPC分类号： H01L21/336 ,  H01L29/49 ,  H01L21/8238

    CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823807 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66583

    摘要： The process rules for manufacturing semiconductor devices such as MOSFET's are modified to provide dual work-function doping following the customary gate sidewall oxidation step, greatly reducing thermal budget and boron penetration concerns. The concern of thermal budget is further significantly reduced by a device structure which allows a reduced gap aspect ratio while maintaining low sheet resistance values. A reduced gap aspect ratio also relaxes the need for highly reflowable dielectric materials and also facilitates the use of angled source-drain (S-D) and halo implants. Also provided is a novel structure and process for producing a MOSFET channel, lateral doping profile which suppresses short channel effects while providing low S-D junction capacitance and leakage, as well as immunity to hot-carrier effects. This also affords the potential for reduction in the contact stud-to-gate conductor capacitance, because borderless contacts can be formed with an oxide gate sidewall spacer. As a result, the S-D junctions can be doped independently of the gate conductor doping, more easily allowing a variety of MOSFET structures.

    摘要翻译： 用于制造半导体器件的方法的规则：如MOSFET的被修改，以提供双功函数掺杂继常规栅侧壁氧化步骤，大大降低热预算和硼渗透的担忧。 热预算的关注被进一步显着，同时保持低的薄层电阻值，其允许降低了的间隙的纵横比的器件结构减小。 从而减小的间隙的纵横比放宽了对高度可回流的介电材料的需求，并且因此便于使用成角度的源极 - 漏极（S-D）和含卤素的注入的。 这样提供了一种用于制造MOSFET沟道，横向掺杂分布，其抑制短沟道效应，而对热载流子效应提供低S-D结电容和漏电流，以及免疫的新颖结构和工艺。 因此这提供减少在接触柱到栅导体的电容的电势，由于无边界接触可以与氧化物栅极侧壁间隔物来形成。 作为结果，S-D结能够掺杂栅导体的掺杂，更方便地允许各种MOSFET结构中的unabhängig。

    Improved process for buried-strap self-aligned to deep storage trench
    2.
    发明公开
    Improved process for buried-strap self-aligned to deep storage trench 审中-公开
    埋深带自对准深埋储沟槽的改进工艺

    公开(公告)号：EP1022782A3

    公开(公告)日：2000-08-23

    申请号：EP00100875.4

    申请日：2000-01-18

    申请人： International Business Machines Corporation ,  Infineon Technologies AG

    发明人： Grüning, Ulrike ,  Mandelman, Jack ,  Radens, Carl

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10861

    摘要： A process for forming a buried strap self-aligned to a deep storage trench. Spacers are formed on walls of a recess over a filled deep trench capacitor and a substrate. A plug is formed in a region between the spacers. Photoresist is deposited over the spacers, the plug, and material surrounding the spacers of the plug. The photoresist is patterned, thereby exposing portions of the plug, the spacers, and the surrounding material. The spacers in the surrounding material not covered by the photoresist are selectively etched, leaving a remaining portion of the spacers. The substrate and the portion of the filled deep trench exposed by the spacer removal are selectively etched. An isolation region is formed in a space created by etching of the spacers, surrounding material, substrate, and filled deep trench.

    摘要翻译： 一种形成与深存储沟槽自对准的掩埋带的工艺。 在填充的深沟槽电容器和衬底上方的凹陷的壁上形成间隔物。 塞子形成在间隔物之间​​的区域中。 光致抗蚀剂沉积在间隔物，插塞和围绕插塞间隔物的材料上。 光致抗蚀剂被图案化，从而暴露插塞，间隔物和周围材料的一部分。 未被光致抗蚀剂覆盖的周围材料中的间隔物被选择性蚀刻，留下间隔物的剩余部分。 衬底和通过间隔件去除而暴露的填充深沟槽的部分被选择性地蚀刻。 隔离区域形成在通过蚀刻间隔物，周围材料，衬底和填充的深沟槽而形成的空间中。

    DRAM trench capacitor cell
    3.
    发明公开
    DRAM trench capacitor cell 审中-公开
    DRAM-Zelle mit Grabenkondensator

    公开(公告)号：EP1017095A3

    公开(公告)日：2005-04-13

    申请号：EP99310310.0

    申请日：1999-12-21

    申请人： Infineon Technologies AG ,  International Business Machines Corporation

    发明人： Radens, Carl ,  Gruening, Ulrike ,  DeBrosse, John ,  Mandelman, Jack

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L27/10876

    摘要： A memory cell formed in a semiconductor body includes a vertical trench (14) with a polysilicon fill (22) as a storage capacitor and a field effect transistor having a source (43) formed in the sidewall of the trench, a drain (42) formed in the semiconductor body (10) and having a surface common with a top surface of the semiconductor body, and having a channel region that includes both vertical and horizontal portions and a polysilicon gate (30) that is in an upper portion of the trench. A process for fabrication provides an insulating oxide layer (24A) at the top of the polysilicon fill portion (22) that serves as the storage node and a dielectric layer (28) that was formed as part of the gate dielectric of the transistor.

    摘要翻译： 形成在半导体本体中的存储单元包括具有作为存储电容器的多晶硅填充物（22）的垂直沟槽（14）和形成在沟槽的侧壁中的源极（43）的场效应晶体管，漏极（42） 形成在所述半导体本体（10）中并且具有与所述半导体主体的顶表面共同的表面，并且具有包括垂直和水平部分的沟道区域和位于所述沟槽的上部的多晶硅栅极（30） 。 一种制造工艺在多晶硅填充部分（22）的顶部提供用作存储节点的绝缘氧化物层（24A）和形成为晶体管的栅极电介质的一部分的电介质层（28）。

    Process for producing transistors having independently adjustable parameters
    5.
    发明公开
    Process for producing transistors having independently adjustable parameters 审中-公开
    一种用于晶体管的与独立的可调参数的制造过程

    公开(公告)号：EP1071125A3

    公开(公告)日：2005-06-01

    申请号：EP00114376.7

    申请日：2000-07-05

    申请人： International Business Machines Corporation ,  Infineon Technologies AG

    发明人： Divakaruni, Rama ,  Gambino, Jeffrey P. ,  Mandelman, Jack ,  Rengarajan, Rajesh

    IPC分类号： H01L21/336 ,  H01L29/49 ,  H01L21/8238

    CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823807 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66583

    摘要： The process rules for manufacturing semiconductor devices such as MOSFET's are modified to provide dual work-function doping following the customary gate sidewall oxidation step, greatly reducing thermal budget and boron penetration concerns. The concern of thermal budget is further significantly reduced by a device structure which allows a reduced gap aspect ratio while maintaining low sheet resistance values. A reduced gap aspect ratio also relaxes the need for highly reflowable dielectric materials and also facilitates the use of angled source-drain (S-D) and halo implants. Also provided is a novel structure and process for producing a MOSFET channel, lateral doping profile which suppresses short channel effects while providing low S-D junction capacitance and leakage, as well as immunity to hot-carrier effects. This also affords the potential for reduction in the contact stud-to-gate conductor capacitance, because borderless contacts can be formed with an oxide gate sidewall spacer. As a result, the S-D junctions can be doped independently of the gate conductor doping, more easily allowing a variety of MOSFET structures.

    Improved process for buried-strap self-aligned to deep storage trench
    7.
    发明公开
    Improved process for buried-strap self-aligned to deep storage trench 审中-公开
    Verbeetes Verfahrenfürein zu einem tiefen Speichergraben selbstjustiertes，vergrabenes Band

    公开(公告)号：EP1022782A2

    公开(公告)日：2000-07-26

    申请号：EP00100875.4

    申请日：2000-01-18

    申请人： International Business Machines Corporation ,  Infineon Technologies AG

    发明人： Grüning, Ulrike ,  Mandelman, Jack ,  Radens, Carl

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10861

    摘要： A process for forming a buried strap self-aligned to a deep storage trench. Spacers are formed on walls of a recess over a filled deep trench capacitor and a substrate. A plug is formed in a region between the spacers. Photoresist is deposited over the spacers, the plug, and material surrounding the spacers of the plug. The photoresist is patterned, thereby exposing portions of the plug, the spacers, and the surrounding material. The spacers in the surrounding material not covered by the photoresist are selectively etched, leaving a remaining portion of the spacers. The substrate and the portion of the filled deep trench exposed by the spacer removal are selectively etched. An isolation region is formed in a space created by etching of the spacers, surrounding material, substrate, and filled deep trench.

    摘要翻译： 一种用于形成与深存储沟槽自对准的掩埋带的工艺。 垫片形成在填充的深沟槽电容器和衬底上的凹部的壁上。 插塞形成在间隔件之间的区域中。 光刻胶沉积在隔离物，插塞和围绕插塞间隔物的材料上。 对光致抗蚀剂进行图案化，从而暴露插头，间隔件和周围材料的部分。 不被光致抗蚀剂覆盖的周围材料中的间隔物被选择性地蚀刻，留下间隔物的剩余部分。 选择性地蚀刻衬底和通过间隔物去除而暴露的填充深沟槽的部分。 在通过蚀刻间隔物，周围的材料，衬底和填充的深沟槽而产生的空间中形成隔离区。

    DRAM trench capacitor cell
    8.
    发明公开
    DRAM trench capacitor cell 审中-公开
    DRAM沟槽电容器单元

    公开(公告)号：EP1017095A2

    公开(公告)日：2000-07-05

    申请号：EP99310310.0

    申请日：1999-12-21

    申请人： Infineon Technologies North America Corp. ,  International Business Machines Corporation

    发明人： Radens, Carl ,  Gruening, Ulrike ,  DeBrosse, John ,  Mandelman, Jack

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L27/10876

    摘要： A memory cell formed in a semiconductor body includes a vertical trench with a polysilicon fill as a storage capacitor and a field effect transistor having a source formed in the sidewall of the trench, a drain formed in the semiconductor body and having a surface common with a top surface of the semiconductor body, and having a channel region that includes both vertical and horizontal portions and a polysilicon gate that is in an upper portion of the trench. A process for fabrication provides an insulating oxide layer at the top of the polysilicon fill portion that serves as the storage node and the polysilicon fill portion that serves as the gate conductor.

    摘要翻译： 形成在半导体本体中的存储单元包括具有作为存储电容器的多晶硅填充物的垂直沟槽和具有形成在沟槽的侧壁中的源极的场效应晶体管，形成在半导体本体中并且具有与 并且具有包括垂直部分和水平部分的沟道区域以及位于沟道上部的多晶硅栅极。 用于制造的工艺在用作存储节点的多晶硅填充部分的顶部和用作栅极导体的多晶硅填充部分处提供绝缘氧化物层。

    DRAM CELL HAVING AN ANNULAR SIGNAL TRANSFER REGION
    10.
    发明公开
    DRAM CELL HAVING AN ANNULAR SIGNAL TRANSFER REGION 审中-公开
    具有环形信号传输领域DRAM单元

    公开(公告)号：EP1135801A1

    公开(公告)日：2001-09-26

    申请号：EP99956237.4

    申请日：1999-11-26

    申请人： International Business Machines Corporation ,  IBM United Kingdom Limited

    发明人： Agahi, Farid ,  Hsu, Louis ,  Mandelman, Jack

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10864 ,  H01L27/10841

    摘要： A memory device in a substrate having a trench with side walls in the substrate includes bit line and word line conductors. Signal storage node has first electrode, second electrode formed within the trench, and node dielectric formed between the electrodes. Signal transfer device has: an annular signal transfer region with outer surface adjacent side walls of the trench, an inner surface, a first and a second end; first diffusion region coupling first end of the signal transfer region to second electrode of the signal storage node; second diffusion region coupling second end of signal transfer region to bit line conductor; a gate insulator coating the inner surface of signal transfer region; and a gate conductor coating the gate insulator and coupled to the word line. Conductive connecting member couples signal transfer region to reference voltage to reduce floating body effects.