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公开(公告)号：EP2400501B1
公开(公告)日：2015-08-12
申请号：EP11171320.2
申请日：2011-06-24
CPC分类号： G11C19/28 , G09G3/3674 , G09G3/3677 , G09G3/3688 , G09G2300/0413 , G09G2300/0465 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08
摘要： A plurality of cascaded unit register circuits (38) which comprises a bidirectional shift register (30) include main stages and dummy stages at the top before the main stages and dummy stages at the bottom after the main stages. A k-th stage outputs a pulse P k in synchronization with a clock signal with a reference point N1 being at H level. The main stages include terminals NSF and NSB for setting N1 to H to which P k - 1 and P k+1 are input, respectively, and terminals NRB and NRF for setting N1 to L level to which P k - 2 and P k+2 are input, respectively. The order of generation of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched. Top dummy stages do not have NRB. Bottom dummy stages do not have NRF.
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2.发明公开Bidirectional shift register and image display device using the same 审中-公开俾路支书记Bildanzeigevorrichtung damit
公开(公告)号：EP2400485A1
公开(公告)日：2011-12-28
申请号：EP11171002.6
申请日：2011-06-22
摘要： A bidirectional shift register outputs pulses from a plurality of cascaded unit register circuits in a shift order which is one of a forward direction and a reverse direction. A λth stage of unit register circuit (38) has two set terminals connected to respective outputs of (λ-1)th and (λ+1)th stages and two reset terminals connected to respective outputs of (λ+2) th and (λ-2) th stages. The unit register circuit (38) sets, when a pulse is input to any one of the set terminals, a reference point N1 to an H level, and, when a pulse is input to any one of the reset terminals, N1 to an L level. The order of phase change of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched.
摘要翻译： 双向移位寄存器以多个级联单元寄存器电路以正向和反向之一的移位顺序输出脉冲。 单元寄存器电路（38）的第三级具有连接到（»-1）和（+ +1）级的相应输出的两个设定端子，以及连接到（+ +）的各个输出的两个复位端子，以及 （»-2）阶段。 当单位寄存器电路（38）将脉冲输入到设定端子中的任一个时，将参考点N1设定为H电平，并且当将脉冲输入到复位端子中的任何一个N1至L 水平。 时钟信号的相位变化顺序根据移位方向反转，开始触发信号是施加到顶级还是下级切换。
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公开(公告)号：EP2400485B1
公开(公告)日：2019-11-20
申请号：EP11171002.6
申请日：2011-06-22
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4.发明授权
公开(公告)号：EP2194636B1
公开(公告)日：2012-02-15
申请号：EP09176844.0
申请日：2009-11-24
发明人： Kasai, Naruhiko , Eriguchi, Takuya , Okada, Yuki , Goto, Mitsuru , Kotani, Yoshihiro , Takada, Naoki
CPC分类号： G09G3/3696 , G09G2330/02 , G09G2330/021 , H02M3/07 , H02M3/156 , H02M2001/0032 , Y02B70/16
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公开(公告)号：EP2400501A1
公开(公告)日：2011-12-28
申请号：EP11171320.2
申请日：2011-06-24
CPC分类号： G11C19/28 , G09G3/3674 , G09G3/3677 , G09G3/3688 , G09G2300/0413 , G09G2300/0465 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08
摘要： A plurality of cascaded unit register circuits (38) which comprises a bidirectional shift register (30) include main stages and dummy stages at the top before the main stages and dummy stages at the bottom after the main stages. A k-th stage outputs a pulse P k in synchronization with a clock signal with a reference point N1 being at H level. The main stages include terminals NSF and NSB for setting N1 to H to which P k - 1 and P k+1 are input, respectively, and terminals NRB and NRF for setting N1 to L level to which P k - 2 and P k+2 are input, respectively. The order of generation of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched. Top dummy stages do not have NRB. Bottom dummy stages do not have NRF.
摘要翻译： 包括双向移位寄存器（30）的多个级联单元寄存器电路（38）包括在主级之前的顶部和在主级之后的底部的虚拟级的主级和虚级。 第k级与参考点N1处于H电平的时钟信号同步地输出脉冲Pk。 主级包括分别用于设置输入Pk-1和Pk + 1的N1至H的端子NSF和NSB，以及用于设置输入Pk-2和Pk + 2的N1至L电平的端子NRB和NRF， 分别。 时钟信号的生成顺序根据移位的方向而反转，并且开关触发信号是被施加到顶层还是底层。 顶级虚拟舞台没有NRB。 底部虚拟舞台没有NRF。
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