公开(公告)号：EP1170865B1

公开(公告)日：2005-08-31

申请号：EP01113682.7

申请日：2001-06-20

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Zama, Hidemasa, 435, Creare-Toshiba-Motosumiyoshi ,  Koizumi, Masayuki ,  Ito, Yukiko ,  Usami, Kimiyoshi ,  Kawabe, Naoyuki ,  Kanazawa, Masahiro ,  Furusawa, Toshiyuki

IPC分类号： H03K19/00 ,  H03K19/094 ,  H01L21/822

CPC分类号： H03K19/01707 ,  H03K19/0016

公开(公告)号：EP1195902B1

公开(公告)日：2010-10-27

申请号：EP01122513.3

申请日：2001-09-21

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Furusawa, Toshiyuki ,  Sonoda, Daisuke ,  Usami, Kimiyoshi ,  Kawabe, Naoyuki ,  Koizumi, Masayuki ,  Zama, Hidemasa ,  Kanazawa, Masahiro

IPC分类号： H03K19/00

CPC分类号： H03K19/0016

公开(公告)号：EP1170865A3

公开(公告)日：2003-07-23

申请号：EP01113682.7

申请日：2001-06-20

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Zama, Hidemasa, 435, Creare-Toshiba-Motosumiyoshi ,  Koizumi, Masayuki ,  Ito, Yukiko ,  Usami, Kimiyoshi ,  Kawabe, Naoyuki ,  Kanazawa, Masahiro ,  Furusawa, Toshiyuki

IPC分类号： H03K19/00 ,  H03K19/094 ,  H01L21/822

CPC分类号： H03K19/01707 ,  H03K19/0016

摘要： There is provided a semiconductor integrated circuit, a logic operation circuit and a flip flop capable of operating at a high speed and having a leak electric current reduced. In a semiconductor integrated circuit according to the present invention, only a gate circuit on a critical path is constituted by an MT gate cell obtained by combining transistors having a low threshold voltage with transistors having a high threshold voltage, and any other gate circuit is constituted by a transistor having a high threshold voltage. Consequently, the gate circuit on the critical path can be operated at a high speed, and the overall leak electric current can be suppressed, thereby reducing the consumption power.

公开(公告)号：EP1195902A3

公开(公告)日：2003-05-21

申请号：EP01122513.3

申请日：2001-09-21

申请人： Kabushiki Kaisha Toshiba

发明人： Furusawa, Toshiyuki ,  Sonoda, Daisuke ,  Usami, Kimiyoshi ,  Kawabe, Naoyuki ,  Koizumi, Masayuki ,  Zama, Hidemasa ,  Kanazawa, Masahiro

IPC分类号： H03K19/00

CPC分类号： H03K19/0016

摘要： A combination circuit (11) is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit (13) connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit (11) is set to an operative state by the control signal immediately before the flip-flop circuit (13) operates in response to the clock signal.

摘要翻译： 组合电路（11）在响应于控制信号向其提供电力的有效状态和其中断电的无效状态之间切换。 连接到组合电路的输入端的触发电路（13）响应时钟信号存储组合电路的输出信号。 组合电路（11）通过在触发器电路（13）响应于时钟信号操作之前的控制信号设置为工作状态。

公开(公告)号：EP1619798A1

公开(公告)日：2006-01-25

申请号：EP05018764.0

申请日：2001-06-20

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Zama, Hedemasa ,  Koizumi, Masayuki, 204,Namamugi-Yuri-Heights ,  Ito, Yukiko ,  Usami, Kimiyoshi ,  Kawabe, Naoyuki, 302,Toshiba-Nakanocho-Apart. ,  Kanazawa, Masahiro ,  Furusawa, Toshiyuki

IPC分类号： H03K19/00 ,  H03K19/094 ,  H01L21/822

CPC分类号： H03K19/01707 ,  H03K19/0016

摘要： There is provided a semiconductor integrated circuit, a logic operation circuit and a flip flop capable of operating at a high speed and having a leak electric current reduced.
In a semiconductor integrated circuit according to the present invention, only a gate circuit on a critical path is constituted by an MT gate cell obtained by combining transistors having a low threshold voltage with transistors having a high threshold voltage, and any other gate circuit is constituted by a transistor having a high threshold voltage. Consequently, the gate circuit on the critical path can be operated at a high speed, and the overall leak electric current can be suppressed, thereby reducing the consumption power.

摘要翻译： 提供了能够高速运转并且漏电流减少的半导体集成电路，逻辑运算电路和触发器。 在根据本发明的半导体集成电路中，仅关键路径上的门电路由通过组合具有低阈值电压的晶体管与具有高阈值电压的晶体管获得的MT门单元构成，并且构成任何其它门电路 通过具有高阈值电压的晶体管。 因此，关键路径上的门电路可以高速运转，可以抑制整体的漏电流，从而降低功耗。

公开(公告)号：EP1195902A2

公开(公告)日：2002-04-10

申请号：EP01122513.3

申请日：2001-09-21

申请人： Kabushiki Kaisha Toshiba

发明人： Furusawa, Toshiyuki ,  Sonoda, Daisuke ,  Usami, Kimiyoshi ,  Kawabe, Naoyuki ,  Koizumi, Masayuki ,  Zama, Hidemasa ,  Kanazawa, Masahiro

IPC分类号： H03K19/00

CPC分类号： H03K19/0016

摘要： A combination circuit (11) is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit (13) connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit (11) is set to an operative state by the control signal immediately before the flip-flop circuit (13) operates in response to the clock signal.

公开(公告)号：EP1170865A2

公开(公告)日：2002-01-09

申请号：EP01113682.7

申请日：2001-06-20

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Zama, Hidemasa, 435, Creare-Toshiba-Motosumiyoshi ,  Koizumi, Masayuki ,  Ito, Yukiko ,  Usami, Kimiyoshi ,  Kawabe, Naoyuki ,  Kanazawa, Masahiro ,  Furusawa, Toshiyuki

IPC分类号： H03K19/00

CPC分类号： H03K19/01707 ,  H03K19/0016

摘要： There is provided a semiconductor integrated circuit, a logic operation circuit and a flip flop capable of operating at a high speed and having a leak electric current reduced.
In a semiconductor integrated circuit according to the present invention, only a gate circuit on a critical path is constituted by an MT gate cell obtained by combining transistors having a low threshold voltage with transistors having a high threshold voltage, and any other gate circuit is constituted by a transistor having a high threshold voltage. Consequently, the gate circuit on the critical path can be operated at a high speed, and the overall leak electric current can be suppressed, thereby reducing the consumption power.

摘要翻译： 提供了能够高速运转并且漏电流减少的半导体集成电路，逻辑运算电路和触发器。 在根据本发明的半导体集成电路中，仅关键路径上的门电路由通过组合具有低阈值电压的晶体管与具有高阈值电压的晶体管获得的MT门单元构成，并且构成任何其它门电路 通过具有高阈值电压的晶体管。 因此，关键路径上的门电路可以高速运转，可以抑制整体的漏电流，从而降低功耗。