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公开(公告)号：EP0301601B1
公开(公告)日：1993-03-03
申请号：EP88112453.1
申请日：1988-08-01
发明人： Goto, Hiroshige
CPC分类号： H04N5/18
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2.发明公开Charge transfer device and its driving method 失效Ladungsübertragungsanordnungund deren Antriebsverfahren。
公开(公告)号：EP0406890A2
公开(公告)日：1991-01-09
申请号：EP90112943.7
申请日：1990-07-06
发明人： Goto, Hiroshige
CPC分类号： G11C27/04 , G11C19/285
摘要： A charge transfer device and its driving method are disclosed such that transfer pulses each having an amplitude substantially equal to that of transfer pulses applied to transfer electrodes at transfer stages before a plurality of successively-arranged transfer stages including a final transfer stage and DC offset levels so decreased gradually as to gradually make shallow the depth of potential wells formed under the transfer electrodes toward the final transfer stage are applied to transfer electrodes (16 n-2 to 16 n ; 17 n-2 to 17 n ) at successively-arranged plural transfer stages including the final stage. Further, a charge transfer device and its driving method are disclosed such that a transfer pulse having an amplitude substantially equal to that of transfer pulses applied to transfer electrodes at transfer stages before the final transfer stage and a DC offset voltage so biased as to allow the depth of potential well formed under the transfer electrodes at the final transfer stage to be shallower than that of potential wells formed under the transfer electrodes at the transfer stages before the final transfer stage is applied to the transfer electrode at the final transfer stage.
摘要翻译： 公开了一种电荷转移装置及其驱动方法，使得转移脉冲各自具有基本上等于在转移阶段转移电极的转移脉冲的幅度基本上等于在包括最终转印阶段和DC偏移水平的多个连续排列的转印阶段之前的转印脉冲 逐渐下降，逐渐变浅，在转移电极向最终转移阶段形成的势阱的深度在连续布置的多个转移阶段施加到转移电极（16n-2至16n; 17n-2至17n），包括 最后阶段。 此外，公开了一种电荷转移装置及其驱动方法，使得具有与在最终转印阶段之前的转印阶段施加到转印电极的转印脉冲的幅度基本相等的转印脉冲和如此偏置的DC偏移电压， 在最后的转印阶段，在转印电极下形成的电位深度比在最后转印阶段施加到转印电极之前的转印阶段下形成在转印电极下的势阱的深度更浅。
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公开(公告)号：EP0301601A3
公开(公告)日：1989-08-09
申请号：EP88112453.1
申请日：1988-08-01
发明人： Goto, Hiroshige
CPC分类号： H04N5/18
摘要： A clamping circuit suitable for an image processing is disclosed. This clamping circuit includes a differential output circuit (13) to which an input signal is applied, series-connected two MOS type gate circuits (14,15) respectively having gate electrodes to which an output signal from the differential output circuit to be clamped and a reference voltage (V REF ) of a target value are applied, and reset circuit (18) including a holding capacitor (17) connected to the drain electrode side of either of the MOS type gate circuits (14,15) to discharge charge in the holding capacitor (17) at the time of beginning of clamping operation. The clamping circuit further includes a current source (16) connected to the junction between the MOS type gate circuits (14,15), charge current flow control circuit (19) for accumulating charge in the holding capacitor (17), and feedback circuit (20) for feeding back a potential of the holding capacitor (17) to the differential output circuit (13). Thus, a small-sized clamping circuit which can perform stable operation is provided.
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4.发明公开Solid image sensor using junction gate type field-effect transistor as pixel 审中-公开Festkörperbildsensormit Verwendung eines Sperrschicht-Feldeffekttransistors als Pixel
公开(公告)号：EP1806785A3
公开(公告)日：2007-07-25
申请号：EP07007781.3
申请日：2002-11-12
发明人： Goto, Hiroshige
IPC分类号： H01L27/146
CPC分类号： H01L27/14603 , H01L27/14679
摘要： Solid-state imager with a plurality of pixels formed in a semiconductor substrate (20). Inside a well region (21) of a first conductive type a source (42) and a drain (41) of the opposite conductive type are formed. Between source (42) and drain (41) a barrier region (43) of the first conductive type is formed. Directly underneath the barrier region is a third semiconductor region (44) of the second conductive type to modulate the field distribution inside the well.
摘要翻译： 源极区（23）和漏极区（22）形成在第一半导体区域（21）的表面区域中。 此外，在第一半导体区域（21）的表面区域中形成连接到漏极区域（22）的第二半导体区域（24）。 在与第二半导体区域（24）连接的第二半导体区域（24）的第一半导体区域（21）内形成第三半导体区域（26），并根据入射光累积信号电荷。 在漏极区域和源极区域之间的第一半导体区域的表面区域中形成第四半导体区域（25）。 此外，这些源极区域，漏极区域，第二半导体区域和第三半导体区域构成像素，并且在像素中的信号电荷的累积期间，信号读出期间和放电期间内，向漏极区域供给不同的电压 信号充电。
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公开(公告)号：EP0301601A2
公开(公告)日：1989-02-01
申请号：EP88112453.1
申请日：1988-08-01
发明人： Goto, Hiroshige
CPC分类号： H04N5/18
摘要： A clamping circuit suitable for an image processing is disclosed. This clamping circuit includes a differential output circuit (13) to which an input signal is applied, series-connected two MOS type gate circuits (14,15) respectively having gate electrodes to which an output signal from the differential output circuit to be clamped and a reference voltage (V REF ) of a target value are applied, and reset circuit (18) including a holding capacitor (17) connected to the drain electrode side of either of the MOS type gate circuits (14,15) to discharge charge in the holding capacitor (17) at the time of beginning of clamping operation. The clamping circuit further includes a current source (16) connected to the junction between the MOS type gate circuits (14,15), charge current flow control circuit (19) for accumulating charge in the holding capacitor (17), and feedback circuit (20) for feeding back a potential of the holding capacitor (17) to the differential output circuit (13). Thus, a small-sized clamping circuit which can perform stable operation is provided.
摘要翻译： 公开了一种适用于图像处理的钳位电路。 该钳位电路包括施加输入信号的差分输出电路（13），串联连接的两个MOS型栅极电路（14,15），分别具有栅极电极，来自差分输出电路的输出信号被钳位到该栅电极， 施加目标值的参考电压（VREF），以及复位电路（18），其包括与MOS型栅极电路（14,15）中的任一个的漏电极侧连接的保持电容器（17），以在 在夹紧操作开始时保持电容器（17）。 钳位电路还包括连接到MOS型栅极电路（14,15）之间的结的电流源（16），用于在保持电容器（17）中累积电荷的充电电流流动控制电路（19）和反馈电路 20），用于将保持电容器（17）的电位反馈到差分输出电路（13）。 因此，提供了可以执行稳定操作的小尺寸钳位电路。
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6.发明公开Solid image sensor using junction gate type field-effect transistor as pixel 审中-公开使用结型栅极型场效应晶体管作为像素的固体图像传感器
公开(公告)号：EP1806785A2
公开(公告)日：2007-07-11
申请号：EP07007781.3
申请日：2002-11-12
发明人： Goto, Hiroshige
IPC分类号： H01L27/146
CPC分类号： H01L27/14603 , H01L27/14679
摘要： A source region (23) and drain region (22) are formed in a surface region of a first semiconductor region (21). Moreover, a second semiconductor region (24) connected to the drain region (22) is formed in the surface region of the first semiconductor region (21). A third semiconductor region (26) is formed in the first semiconductor region (21) under the second semiconductor region (24), connected to the second semiconductor region (24), and accumulates signal charges in accordance with an incident light. A fourth semiconductor region (25) is formed in the surface region of the first semiconductor region between the drain region and source region. Moreover, these source region, drain region, second semiconductor region, and third semiconductor region constitute a pixel, and different voltages are supplied to the drain region in an accumulation period of the signal charges in the pixel, signal readout period, and discharge period of the signal charges.
摘要翻译： 源区（23）和漏区（22）形成在第一半导体区（21）的表面区中。 此外，连接到漏极区（22）的第二半导体区（24）形成在第一半导体区（21）的表面区中。 第三半导体区域（26）形成在第二半导体区域（24）下方的第一半导体区域（21）中，连接到第二半导体区域（24），并且根据入射光积累信号电荷。 第四半导体区域（25）形成在漏极区域和源极区域之间的第一半导体区域的表面区域中。 此外，这些源极区域，漏极区域，第二半导体区域和第三半导体区域构成像素，并且在像素中的信号电荷的累积时段，信号读出时段和放电时段中将不同的电压提供给漏区 信号收费。
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7.发明公开Solid-state image sensor using junction gate type field-effect transistor as pixel 审中-公开Festkörperbildsensormit Sperrschicht-Feldeffekttransistor als Pixel
公开(公告)号：EP1801878A2
公开(公告)日：2007-06-27
申请号：EP07007780.5
申请日：2002-11-12
发明人： Goto, Hiroshige
IPC分类号： H01L27/146
CPC分类号： H01L27/14603 , H01L27/14679
摘要： Solid-state imager with a plurality of pixels formed in a semiconductor substrate (20). Inside a well region (21) of a first conductive type a source (42) and a drain (41) with the opposite type are formed. Between source (42) and drain (41) a barrier region (43) of the first conductive type is formed. Directly underneath the barrier region is a third semiconductor region (44) of the second conductive type to modulate the field distribution inside the well. The accumulated charges in the well can be reset using two additional regions of the first conductive type (54,55).
摘要翻译： 具有形成在半导体衬底（20）中的多个像素的固态成像器。 在第一导电类型的阱区（21）内形成具有相反类型的源极（42）和漏极（41）。 在源极（42）和漏极（41）之间形成有第一导电类型的阻挡区域（43）。 阻挡区域的正下方是第二导电类型的第三半导体区域（44），用于调制阱内部的场分布。 可以使用第一导电类型的两个附加区域（54,55）来重置阱中的累积电荷。
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8.发明授权Manufacturing method of semiconductor device having CCD and peripheral circuit 失效具有CCD和外围电路的半导体器件的制造方法
公开(公告)号：EP0305742B1
公开(公告)日：1992-06-03
申请号：EP88112319.4
申请日：1988-07-29
发明人： Goto, Hiroshige
IPC分类号： H01L21/82
CPC分类号： H01L21/8234
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9.发明公开Solid-state image sensor using junction gate type field-effect transistor as pixel 审中-公开与JFET固态图像传感器的像素
公开(公告)号：EP1801878A3
公开(公告)日：2007-07-04
申请号：EP07007780.5
申请日：2002-11-12
发明人： Goto, Hiroshige
IPC分类号： H01L27/146
CPC分类号： H01L27/14603 , H01L27/14679
摘要： Solid-state imager with a plurality of pixels formed in a semiconductor substrate (20). Inside a well region (21) of a first conductive type a source (42) and a drain (41) with the opposite type are formed. Between source (42) and drain (41) a barrier region (43) of the first conductive type is formed. Directly underneath the barrier region is a third semiconductor region (44) of the second conductive type to modulate the field distribution inside the well. The accumulated charges in the well can be reset using two additional regions of the first conductive type (54,55).
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公开(公告)号：EP0406890B1
公开(公告)日：1995-09-27
申请号：EP90112943.7
申请日：1990-07-06
发明人： Goto, Hiroshige
CPC分类号： G11C27/04 , G11C19/285
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