公开(公告)号：EP0087754A2

公开(公告)日：1983-09-07

申请号：EP83101781.9

申请日：1983-02-23

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Fujii, Syuso 313 Toshiba-Komukai-jutaku ,  Saito, Shozo ,  Natori, Kenji ,  Furuyama, Tohru

IPC分类号： G11C11/24 ,  G11C5/00 ,  G11C8/00

CPC分类号： G11C11/4091 ,  G11C5/025 ,  G11C11/407 ,  G11C11/408 ,  G11C11/4087 ,  G11C11/4096

摘要： A semiconductor dynamic memory device includes a plurality of memories (12-1 to 12-4), row decoders (16-1 to 16-4) for selecting the row of the memories, column decoders (14-1 and 14-2) for selecting the column of memories, and sense amplifier circuits (18-1 to 18-4) connected to the memories, respectively. The dynamic memory device further has a driving circuit (24) for selectively activating some of the sense amplifier circuits (18-1 to 18-4) in accordance with the content of a predetermined bit of row address data supplied to the row decoders.

公开(公告)号：EP0087754B1

公开(公告)日：1989-05-10

申请号：EP83101781.9

申请日：1983-02-23

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Fujii, Syuso 313 Toshiba-Komukai-jutaku ,  Saito, Shozo ,  Natori, Kenji ,  Furuyama, Tohru

IPC分类号： G11C11/24 ,  G11C5/00 ,  G11C8/00

CPC分类号： G11C11/4091 ,  G11C5/025 ,  G11C11/407 ,  G11C11/408 ,  G11C11/4087 ,  G11C11/4096

公开(公告)号：EP0035793B1

公开(公告)日：1985-07-24

申请号：EP81101768.0

申请日：1981-03-10

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Ohuchi, Kazunori ,  Ogura, Mitsugi ,  Natori, Kenji

IPC分类号： H01L23/52 ,  H01L29/52 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L23/522 ,  H01L23/535 ,  H01L29/41725 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP0035793B2

公开(公告)日：1989-08-23

申请号：EP81101768.0

申请日：1981-03-10

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Ohuchi, Kazunori ,  Ogura, Mitsugi ,  Natori, Kenji

IPC分类号： H01L23/52 ,  H01L29/52 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L23/522 ,  H01L23/535 ,  H01L29/41725 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP0087754A3

公开(公告)日：1986-02-12

申请号：EP83101781

申请日：1983-02-23

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Fujii, Syuso 313 Toshiba-Komukai-jutaku ,  Saito, Shozo ,  Natori, Kenji ,  Furuyama, Tohru

IPC分类号： G11C11/24 ,  G11C05/00 ,  G11C08/00

CPC分类号： G11C11/4091 ,  G11C5/025 ,  G11C11/407 ,  G11C11/408 ,  G11C11/4087 ,  G11C11/4096

摘要： A semiconductor dynamic memory device includes a plurality of memories (12-1 to 12-4), row decoders (16-1 to 16-4) for selecting the row of the memories, column decoders (14-1 and 14-2) for selecting the column of memories, and sense amplifier circuits (18-1 to 18-4) connected to the memories, respectively. The dynamic memory device further has a driving circuit (24) for selectively activating some of the sense amplifier circuits (18-1 to 18-4) in accordance with the content of a predetermined bit of row address data supplied to the row decoders.

公开(公告)号：EP0035793A1

公开(公告)日：1981-09-16

申请号：EP81101768.0

申请日：1981-03-10

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Ohuchi, Kazunori ,  Ogura, Mitsugi ,  Natori, Kenji

IPC分类号： H01L23/52 ,  H01L29/52 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L23/522 ,  H01L23/535 ,  H01L29/41725 ,  H01L2924/0002 ,  H01L2924/00

摘要： A MOS transistor integrated circuit device has at least one interconnection layer (17, 18) crossing the source and drain regions (11, 12) of a MOS transistor such that it overlies these source and drain regions. An electrical conductive layer (29, 30) is formed on the surface of at least one of the source and drain regions (11, 12) of the MOS transistor. The electrical conductive layer crosses the interconnection layer with an insulating layer therebetween such that it underlies the interconnection layer. The electrical conductive layer is separated from source and drain takeout electrodes (15,14) and electrically insulated from the interconnection layer.

摘要翻译： MOS晶体管集成电路器件具有至少一个与MOS晶体管的源极和漏极区（11,12）交叉的互连层（17,18），使得其覆盖这些源极和漏极区。 在MOS晶体管的源极和漏极区（11,12）中的至少一个的表面上形成导电层（29,30）。 导电层穿过互连层，其间具有绝缘层，使得其位于互连层之下。 导电层与源极和漏极取出电极（15,14）分开并与互连层电绝缘。