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    Semiconductor memory device having means for replacing defective memory cells
    1.
    发明公开
    Semiconductor memory device having means for replacing defective memory cells 失效
    一种半导体存储器，包括：用于替换有缺陷的存储单元

    公开(公告)号：EP0686980A1

    公开(公告)日：1995-12-13

    申请号：EP95111838.9

    申请日：1990-01-30

    申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

    发明人： Kasa, Yasushi, c/o Fujitsu Limited ,  Takemae, Yoshihiro, c/o Fujitsu Limited ,  Nagasawa, Masanori, c/o Fujitsu Limited ,  Arayama, Yuji, c/o Fujitsu Limited ,  Terui, Akira, c/o Fujitsu Limited ,  Araki, Sunao c/o Fujitsu Ltd.,

    IPC分类号： G11C29/00 ,  G06F11/20

    CPC分类号： G11C29/76 ,  G06F11/006 ,  G11C11/005 ,  G11C11/407 ,  G11C17/16 ,  G11C29/822

    摘要： A semiconductor memory device comprises a first memory (16, 70, 201-208, 321, 420, 501) comprising memory cells for prestoring fixed data, a decoder (14, 15, 71, 72, 209-216, 225-228, 302, 305, 505, 506) for decoding an input address and for reading out a fixed data from the first memory based on a decoded input address, a second memory (23, 82, 235, 322, 331, 411, 502, 503) for storing a data identical to that prestored in a defective memory cell of the first memory, where the second memory comprising programmable non-volatile memory cells, a discriminating part (13, 75, 76, 96, 308, 309, 426, 522, 523, 531) including a third memory (63, 64, 73, 74, 93, 94, 95, 307, 423, 504) for storing a redundant address of each defective memory cell of the first memory for discriminating whether or not the input address coincides with the redundant address and for outputting a discrimination signal when the input address coincides with the redundant address, and a selecting part (25, 80, 305, 309, 426, 506) supplied with data read out from the first and second memories for normally outputting the data read out from the first memory and selectively outputting the data from the second memory when the discrimination signal is received from the discriminating part.

    摘要翻译： 一种半导体存储器件包括包含用于的Presto环固定数据存储器单元的第一存储器（16，70，201-208，321，420，501），解码器（14，15，71，72，209-216，225-228， 302，305，505，506），用于输入地址的解码和用于从基于经解码的输入地址，第二存储器（23，82，235，322，331，411，502，503中的第一存储器中读出的固定数据 ），用于存储与在所述第一存储器中，有缺陷的存储单元并预先存储一个数据，其中所述第二存储器包括可编程非易失性存储器单元，判别部（13，75，76，96，308，309，426，522 ，523，531）包括用于识别存储在第一存储器中的每个有缺陷的存储单元的冗余地址的第三存储器（63，64，73，74，93，94，95，307，423，504）是否将 输入地址与所述冗余地址和用于输出铃声当输入地址与所述冗余地址，和一个选择部分（25，80，305，309重合一致的识别信号， 426，506）提供数据从所述第一存储器和第二存储器中读出用于正常地输出婷将数据从第一存储器和选择性地输出婷从第二存储器当从判别部所接收的识别信号中读出的数据。

    DRAM controller
    2.
    发明公开
    DRAM controller 失效
    DRAM控制器

    公开(公告)号：EP0383195A3

    公开(公告)日：1992-03-04

    申请号：EP90102518.9

    申请日：1990-02-08

    申请人： Kabushiki Kaisha TEC

    发明人： Takahashi, Toshiyasu

    IPC分类号： G11C11/407 ,  G11C11/409 ,  G11C7/00

    CPC分类号： G11C11/407 ,  G11C11/4096

    摘要： A DRAM controller comprises an address output con­troller (30) for transferring an address-designating signal to a dynamic RAM, a data output controller (32, 34, 36) for transferring data to be written into and read-out from that memory region of the dynamic RAM which is designated by the address-designating signal, and a control circuit responsive to a mode-designating signal for generating various control signals corre­sponding to an access mode of the dynamic RAM designated by the mode-designating signal, and supplying the con­trol signals to the dynamic RAM, address output control­ler (30), and data output controller (32, 34, 36) in a predetermined sequence. In the DRAM controller, the con­trol circuit includes a signal-generating unit (50B) for generating the control signals in a specific access mode which requires an access time longer than the machine cycle of a processor for generating the address-­designating signal, the data to be written, and the mode-designating signal, and for delaying the generating of the control signals every time the designation of the specific access mode is repeated.

    摘要翻译： 一种DRAM控制器包括：地址输出控制器（30），用于将地址指定信号传送给动态RAM;数据输出控制器（32,34,36），用于将数据写入和读出 由地址指定信号指定的动态RAM和响应于模式指定信号的控制电路，用于产生与由模式指定信号指定的动态RAM的访问模式相对应的各种控制信号，并且提供控制 以预定顺序向动态RAM，地址输出控制器（30）和数据输出控制器（32,34,36）发送信号。 在DRAM控制器中，控制电路包括用于以特定访问模式产生控制信号的信号产生单元（50B），该特定访问模式需要比用于产生地址指定信号的处理器的机器周期更长的访问时间， 以及模式指定信号，并且每当重复指定特定访问模式时延迟控制信号的产生。

    Computer memory
    5.
    发明公开
    Computer memory 失效
    电脑记忆

    公开(公告)号：EP0109298A3

    公开(公告)日：1986-07-02

    申请号：EP83306931

    申请日：1983-11-14

    申请人： DATA GENERAL CORPORATION

    发明人： Ziegler, Michael ,  Marshall, Peter G. ,  Whipple, David L.

    IPC分类号： G06F13/00 ,  G11C11/40

    CPC分类号： G06F12/0607 ,  G11C11/407

    摘要： Selection logic (1) responds to 7 out of 22 address bits on a bus (19) to select the module by providing a signal SETRAS, delayed by a signal PRECHG if the same row is address twice in succession. SETRAS generates a row address strobe RAS, a recognition signal ANYRAS and, after a delay (11), a column address signal CAS 16 address bits held in a latch (3) are multiplexed 8 bits at a time a multiplexer (4) and, in synchronism with RAS and CAS select locations in even and odd memory arrays (16 and 17). Two more address bits and selection logic (20) select between four planes in each array. The memory controller responds to the recognition signal ANYRAS to provide an output strobe DOUTSTB - DOUTLTCH to enter both read out words into latches (7, 8). Either (or both in sequence) of further signals from the controller DRVDOUTO, cause one or both words to be read out in sequence to the data bus (18).

    Semiconductor memory device having means for replacing defective memory cells
    7.
    发明公开
    Semiconductor memory device having means for replacing defective memory cells 失效
    一种半导体存储器，包括装置，用于替换有缺陷的存储单元。

    公开(公告)号：EP0383452A2

    公开(公告)日：1990-08-22

    申请号：EP90300935.5

    申请日：1990-01-30

    申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

    发明人： Kasa, Yasushi ,  Takemae, Yoshihiro ,  Nagasawa, Masanori ,  Arayama, Yuji ,  Terui, Akira ,  Araki, Sunao

    IPC分类号： G06F11/20 ,  G11C11/407 ,  G11C17/16

    CPC分类号： G11C29/76 ,  G06F11/006 ,  G11C11/005 ,  G11C11/407 ,  G11C17/16 ,  G11C29/822

    摘要： A semiconductor memory device comprises a first memory (16, 70, 201-208, 321, 420, 501) comprising memory cells for prestoring fixed data, a decoder (14, 15, 71, 72, 209-216, 225-228, 302, 305, 505, 506) for decoding an input address and for reading out a fixed data from the first memory based on a decoded input address, a second memory (23, 82, 235, 322, 331, 411, 502, 503) for storing a data identical to that prestored in a defective memory cell of the first memory, where the second memory comprising programmable non-volatile memory cells, a discriminating part (13, 75, 76, 96, 308, 309, 426, 522, 523, 531) including a third memory (63, 64, 73, 74, 93, 94, 95, 307, 423, 504) for storing a redundant address of each defective memory cell of the first memory for discriminating whether or not the input address coincides with the redundant address and for outputting a discrimination signal when the input address coincides with the redundant address, and a selecting part (25, 80, 305, 309, 426, 506) supplied with data read out from the first and second memories for normally outputting the data read out from the first memory and selectively outputting the data from the second memory when the discrimination signal is received from the discriminating part.

    摘要翻译： 一种半导体存储器件包括包含用于的Presto环固定数据存储器单元的第一存储器（16，70，201-208，321，420，501），解码器（14，15，71，72，209-216，225-228， 302，305，505，506），用于输入地址的解码和用于从基于经解码的输入地址，第二存储器（23，82，235，322，331，411，502，503中的第一存储器中读出的固定数据 ），用于存储与在所述第一存储器中，有缺陷的存储单元并预先存储一个数据，其中所述第二存储器包括可编程非易失性存储器单元，判别部（13，75，76，96，308，309，426，522 ，523，531）包括用于识别存储在第一存储器中的每个有缺陷的存储单元的冗余地址的第三存储器（63，64，73，74，93，94，95，307，423，504）是否将 输入地址与所述冗余地址和用于输出铃声当输入地址与所述冗余地址，和一个选择部分（25，80，305，309重合一致的识别信号， 426，506）提供数据从所述第一存储器和第二存储器中读出用于正常地输出婷将数据从第一存储器和选择性地输出婷从第二存储器当从判别部所接收的识别信号中读出的数据。

    Memory refresh control system upon connection of extension unit
    10.
    发明公开
    Memory refresh control system upon connection of extension unit 失效
    SpeicherauffrischungssteuerschaltungsystemwährendVerbindung mit einer Erweiterungseinheit。

    公开(公告)号：EP0484760A2

    公开(公告)日：1992-05-13

    申请号：EP91118196.4

    申请日：1991-10-24

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Iizuka, Emiko, c/o Intellectual Property Division ,  Nakajima, Shuzo, c/o Intellectual Property Div.

    IPC分类号： G11C11/406 ,  G11C11/407

    CPC分类号： G11C11/407 ,  G11C11/406 ,  G11C11/4076

    摘要： In a portable computer having an extension bus connector connected to a system bus, and a memory connected to an internal bus, and requiring a refresh operation, whether or not an extension unit is connected to the extension bus connector is checked. When the extension unit is connected to the extension bus connector, a refresh signal is output onto the system bus. When the extension unit is not connected to the extension bus connector, the refresh signal is output onto the internal bus. Only when the extension unit is connected to the extension bus connector, the refresh signal is output onto the system bus. When the refresh cycle of a memory incorporated in the portable computer is longer than that of a memory connected to the extension unit, the presence/absence of connection of the extension unit is detected, and a refresh mode is set to be a normal refresh mode.

    摘要翻译： 在具有连接到系统总线的扩展总线连接器和连接到内部总线的存储器并且需要刷新操作的便携式计算机中，检查扩展单元是否连接到扩展总线连接器。 当扩展单元连接到扩展总线连接器时，刷新信号被输出到系统总线上。 当扩展单元未连接到扩展总线连接器时，刷新信号被输出到内部总线上。 只有当扩展单元连接到扩展总线连接器时，刷新信号才会输出到系统总线上。 当结合在便携式计算机中的存储器的刷新周期长于连接到扩展单元的存储器的刷新周期时，检测到扩展单元的连接的存在/不存在，并且将刷新模式设置为正常刷新模式 。