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公开(公告)号：EP1728152A2
公开(公告)日：2006-12-06
申请号：EP05708837.9
申请日：2005-02-24
IPC分类号： G06F9/38
CPC分类号： G06F9/3871 , G06F1/3203 , G06F21/755
摘要： There is provided an electronic circuit that is harder to crack using power analysis techniques, the electronic circuit comprising first and second pipeline stages and a latch positioned between the pipeline stages; wherein the electronic circuit is adapted to operate in a normal mode in which the latch is opened and closed in response to an enable signal, and a reduced mode in which the latch is held open to reduce a current peak associated with the opening and closing of the latch.
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公开(公告)号：EP1745367A2
公开(公告)日：2007-01-24
申请号：EP05732298.4
申请日：2005-04-21
IPC分类号： G06F9/38
CPC分类号： G06F9/3824 , G06F9/3855 , G06F9/3871
摘要： A data processing circuit contains a register file (17) with a write port and a pipeline of instruction processing stages (10a-d). A timing circuit (14) is arranged to time transfer of instruction dependent information between the stages at mutually different time points, so that processing of successive instructions in respective stages partially overlaps. A first and a second one of the stages (10c, d) are in series in the pipeline. Each of the first and a second one of the stages has a result output for writing a result to the write port, if instruction dependent information in the stage concerned (10c, d) requires writing. A write sequencing circuit (144) performs write tests alternately for instruction dependent information in the first and second one of the stages (10c, d). When the write sequencing circuit (144) performs the write test for a particular one of the stages (10c, d), it tests whether the instruction dependent information in the particular one of the stages (10c, d) requires writing of a result. If so, the write sequencing circuit (144), delays transfer of new instruction dependent information through the pipeline (10a-d) to the particular one of the stages (10c,d) until the write port has been committed to writing the result before any results that the write port is subsequently committed to write.
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公开(公告)号：EP1728083A2
公开(公告)日：2006-12-06
申请号：EP05703033.0
申请日：2005-02-24
IPC分类号： G01R31/28
CPC分类号： G06F11/2236 , G01R31/31723 , G01R31/318541
摘要： An electronic circuit is provided that comprises first and second combinational logic blocks and a latch positioned between the combinational logic blocks; wherein the electronic circuit is adapted to operate in a normal mode in which the latch is opened and closed in response to an enable signal, and a test mode in which the latch is held open.
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公开(公告)号：EP1721231A1
公开(公告)日：2006-11-15
申请号：EP05702930.8
申请日：2005-02-09
CPC分类号： H04L9/003 , G06F9/3017 , G06F21/75 , G06F21/755 , H04L2209/08
摘要： The invention relates to an electronic device for cryptographic processing, having at least two electronic circuits (IC, CC, CP) coupled via a connection means, wherein the connection means is arranged for transferring data signals between the two electronic circuits. The electronic device further has a monitoring circuit (401) arranged to monitor a deviation in the capacitance of the connection means. In case the deviation exceeds a predetermined value an alert signal (411) is generated.
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公开(公告)号：EP1728151A2
公开(公告)日：2006-12-06
申请号：EP05708836.1
申请日：2005-02-24
IPC分类号： G06F9/38
CPC分类号： G06F9/3871 , G06F9/3867
摘要： There is provided an electronic circuit adapted to process a plurality of types of instruction, the electronic circuit comprising first and second pipeline stages and a latch positioned between the pipeline stages; wherein the electronic circuit is adapted to operate in a normal mode when processing a first type of instruction in which the latch is opened and closed in response to an enable signal, and a reduced mode when processing a second type of instruction in which the latch is held open so that the instruction propagates through the first and second pipeline stages without being stored in the latch; and wherein the first type of instruction requires processing by the first and second pipeline stages and the second type of instruction requires processing by the second pipeline stage.
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公开(公告)号：EP1687825A1
公开(公告)日：2006-08-09
申请号：EP04770360.8
申请日：2004-11-03
CPC分类号： G06F1/3243 , G06F1/3203 , G06F1/3275 , G11C7/1006 , G11C7/1045 , G11C2207/104 , Y02D10/14 , Y02D10/152
摘要： An electronic circuit is provided that comprises a plurality of storage elements ( 101 - 105 ) arranged for storing of data elements, and a plurality of processing elements. The plurality of processing elements processes the data elements stored in the storage elements. In operation, the points in time at which respective storage elements load their data elements are mutually different in order to meet a maximum allowable value of the power consumption peaks.
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公开(公告)号：EP1665008A2
公开(公告)日：2006-06-07
申请号：EP04769880.8
申请日：2004-08-30
CPC分类号： G06F15/8053 , G06F1/32
摘要： A chain of processing element (l0a, 10, 10b) with a logic circuit (14) and a storage element (12) is provided. The storage elements (12) of all except a final processing element (10b) in the chain have one or more outputs coupled to the logic circuit (14) of a next processing element (10a, 10, l 0b) in the chain. A timing circuit (16) controls respective loading time points at which the storage elements (12) load data from the logic circuits (14) in respective ones of the processing elements (10a, 10, 10b). The data is loaded progressively later in processing elements (10a, 10, 10b) that successively precede one another in the chain. The time interval between successive loading time points of the final processing element (l0b) includes loading time points of loading all processing elements (l0a, 10) other than the final processing element (10).
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