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公开(公告)号：EP1297434B1
公开(公告)日：2005-04-20
申请号：EP01960346.3
申请日：2001-06-20
IPC分类号： G06F13/40
CPC分类号： G06F13/4018
摘要： This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile, so-called flash memory into an ICs. Such a flash memory may be integrated by providing a dedicated flash bus which operationally links the flash memory with one or more microprocessors on the IC. Unfortunately, flash memories have relatively long access times compared to usual modern microprocessors. To achieve that the flash memory keeps pace with the microprocessor(s), a dedicated flash bus (2) links the flash memory (1) to the microprocessor (3), said flash bus (2) having a width m which is greater than the width n of the microprocessor's data bus (8). Preferably, width m is a multiple of width n. A plurality of intermediate storage registers (4) connects the flash bus (2) with the data bus (8) of the microprocessor (3) for performing the width conversion. These intermediate storage registers (4), together with an additional tag register (5), may serve as cache for the microprocessor's data requests, further increasing the potential speed of the IC.
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公开(公告)号：EP1317712A1
公开(公告)日：2003-06-11
申请号：EP01971955.8
申请日：2001-08-23
发明人： KOCH, Stefan , GELKE, Hans-Joachim , HERTWIG, Axel
CPC分类号： G06F13/4004 , G06F13/28 , G06F15/167
摘要： A system (15) comprising at least two integrated processors (P1 and P2). These two processors (P1 and P2) are operably connected via a communication channel (17) for exchanging information. One processor (P1) has a processor bus (10), a shareable unit (13), and a DMA unit (11) with an external DMA channel (12). The DMA unit (11) and the shareable unit (13) are connected to the processor bus (10). The other processor (P2) has an access unit (21) which is connectable to the external DMA channel (12) of the DMA unit (11). Due to this arrangement, a communication channel (17) can be established from the access unit (21) to the shareable unit (13) via the external DMA channel (12), the DMA unit (11), and the processor bus (10).
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公开(公告)号：EP1203379A1
公开(公告)日：2002-05-08
申请号：EP01953172.2
申请日：2001-06-20
发明人： GELKE, Hans-Joachim , HERTWIG, Axel , KOCH, Stefan
CPC分类号： G11C16/102
摘要： This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile flash memory (7) into an IC. To integrate such a flash memory into an IC raises some problems which are solved by providing a dedicated flash bus (3) which operationally links the flash memory (7) with one or more microprocessors (1, 2) on the IC. Preferably, the flash bus (3) controls the flash-memory-specific commands and has a width greater than, in particular a multiple of, the width of the microprocessor (1, 2) and/or the flash memory (7) to compensate for the relatively slow access time of the flash memory. It is especially advantageous to structure the system as a master/slave bus system for operating the flash memory (7) and to link the flash bus via bridges (4, 5, 6) to the microprocessor/s (1, 2,) and through a shell (8) to the flash memory (7). For operating such a system, a flash bus arbiter (9) may be necessary or advantageous.
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4.发明公开
公开(公告)号：EP1535169A2
公开(公告)日：2005-06-01
申请号：EP03765224.5
申请日：2003-07-16
IPC分类号： G06F13/40
CPC分类号： G06F13/4027 , G06F13/28
摘要： System comprising at least two integrated processors (P1 and P2). These two processors (P1 and P2) are operably connected via two bi-directional communication channels for exchanging information. For establishing the bi-directional communication channels, the system comprises a first processor bus (10) to which the first processor (P1) is connected, a first direct memory access unit (45), a first programmable unit (34), and a first shareable unit (13). The programmable unit (34) can be programmed by the first processor (P1). Also comprised is a second processor bus (20), the second processor (P2) being connectable to the second processor bus (20), a second direct memory access unit (35), and a second programmable unit (44). Said second programmable unit (44) is programmable by the second processor (P2).
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5.发明公开IMPROVED ERROR CORRECTION SCHEME FOR USE IN FLASH MEMORY ALLOWING BIT ALTERABILITY 审中-公开完善的纠错方法与BITÄNDERUNGSERMÖGLICHKEIT闪存
公开(公告)号：EP1399819A2
公开(公告)日：2004-03-24
申请号：EP02720402.3
申请日：2002-04-12
发明人： GAPPISCH, Steffen , BAGGEN, Constant, P., M., J. , SLENTER, Andre, G., J. , GELKE, Hans-Joachim
IPC分类号： G06F11/10
CPC分类号： G06F11/1068
摘要： A system (70) comprising a microprocessor (74), a data bus (75) for writing data into a Flash memory device (71) and a data bus (75) for reading data from the Flash memory device (71). The Flash memory device (71) comprises an error correction encoder (72), a Flash memory (71), an error correction decoder (73), and a Flash data bus (75) for interconnecting the error correction encoder (72), the Flash memory (71), and the error correction decoder (73). The data, when being processed by the error correction encoder (72) are converted into a word that comprises a status word (51), a data word (52), and a redundancy word (53). This approach enables error correction with single-bit alterability.
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公开(公告)号：EP1297434A1
公开(公告)日：2003-04-02
申请号：EP01960346.3
申请日：2001-06-20
IPC分类号： G06F13/40
CPC分类号： G06F13/4018
摘要： This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile, so-called flash memory into an ICs. Such a flash memory may be integrated by providing a dedicated flash bus which operationally links the flash memory with one or more microprocessors on the IC. Unfortunately, flash memories have relatively long access times compared to usual modern microprocessors. To achieve that the flash memory keeps pace with the microprocessor(s), a dedicated flash bus (2) links the flash memory (1) to the microprocessor (3), said flash bus (2) having a width m which is greater than the width n of the microprocessor's data bus (8). Preferably, width m is a multiple of width n. A plurality of intermediate storage registers (4) connects the flash bus (2) with the data bus (8) of the microprocessor (3) for performing the width conversion. These intermediate storage registers (4), together with an additional tag register (5), may serve as cache for the microprocessor's data requests, further increasing the potential speed of the IC.
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公开(公告)号：EP1604288A1
公开(公告)日：2005-12-14
申请号：EP04716680.6
申请日：2004-03-03
IPC分类号： G06F13/40
CPC分类号： G06F13/4059
摘要： The data processing device according to the invention comprises a first processing unit ( 1 ) linked to a first bus ( 5 ), a second processing unit ( 2 ) linked to a second bus ( 6 ), a first bus master ( 3 ) linked to the first bus ( 5 ), a second bus master ( 4 ) linked to the second bus ( 6 ), a first and a second communication channel ( 7, 20, 8, 21 ) linking the first and the second bus master ( 3, 4 ) with each other, and a control unit ( 9 ) controlling the data transfer between the first and the second bus master ( 3, 4 ) via the first and the second communication channel ( 7, 20, 8, 21 ).
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8.发明公开NON-VOLATILE MEMORY ARRANGEMENT AND METHOD IN A MULTIPROCESSOR DEVICE 审中-公开DEVICE AND METHOD FOR非易失性存储器中多处理器单元
公开(公告)号：EP1412864A1
公开(公告)日：2004-04-28
申请号：EP02743575.9
申请日：2002-07-08
IPC分类号： G06F13/16
CPC分类号： G06F13/1689 , G06F13/1663 , Y02D10/14
摘要： This invention relates to multiprocessor arrangements with shared non-volatile memory and the design of the access control of this memory, in particular to such memories embedded or integrated into circuits (ICs) as used in mobile phones, PDAs or laptop computers. To reduce power consumption, the processor clock rates are often varied depending on the current performance requirements. Differing clock rates of processors sharing a non-volatile memory leads to relatively long read access times of the latter, since the particular microprocessor fetching the data from the memory is usually halted until the data are available. When dual or multi-port non-volatile memory and multiple asynchronous clocks are used, access times are even longer since clock synchronization between the ports is necessary. The present invention overcomes this problem by providing a plurality of wait timers, preferably one dedicated to each processor, advantageously each being clocked synchronously with its associated processor. This shortens the access times considerably and thus improves overall performance without power penalty.
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公开(公告)号：EP1295295A1
公开(公告)日：2003-03-26
申请号：EP01940586.9
申请日：2001-06-20
IPC分类号： G11C7/10
CPC分类号： G11C7/10 , G11C16/10 , G11C2207/104
摘要： This invention relates to the structure and design of integrated circuits (ICs), in particular to the embedding or integration of a non-volatile, so-called flash memory into ICs. To solve the issues created by speed differrences of the embedded flash memory compared to the other components on an IC, in particular the microprocessor and/or other memory on the IC, a specific writing interface is provided for the flash memory which makes the latter appear like standard memory from a software viewpoint. This writing interface includes a bank of registers (2) between flash memory (7) and microprocessor (6), essentially being operated by a write controller (1) and a flash bus arbiter (8) and acting, in principle, as a intermediate buffering mechanism controlled by a state machine.
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