公开(公告)号：EP0457150A2

公开(公告)日：1991-11-21

申请号：EP91107314.6

申请日：1991-05-06

申请人： LSI LOGIC CORPORATION

发明人： Wong, Anthony Y. ,  Tam, Anna ,  Wong, Daniel

IPC分类号： H01L27/118 ,  H01L27/02

CPC分类号： H01L27/11896

摘要： A repeating cell structure in a semiconductor substrate for a BiCMOS logic gate array. The cell structure has three regions shaped as columns. The first columnar region is a P-well and has four vertically aligned active areas of N-type material formed within the columnar region. Each of the active areas has two gate electrodes to form two NMOS transistors. Similarly the second columnar region is a N-well and has four vertically aligned active areas of P-type material. Each such active region forms two PMOS transistors. The third column has two bipolar transistors, each with collector, base and emitter regions vertically aligned. The resulting BiCMOS logic array permits a flexible location of macrocells, which results in a compact implementation of the resulting integrated circuit.

摘要翻译： BiCMOS逻辑门阵列的半导体衬底中的重复单元结构。 电池结构具有三个形状为列的区域。 第一柱状区域是P阱，并且在柱状区域内形成有四个垂直排列的N型材料的有源区。 每个有源区具有两个栅电极以形成两个NMOS晶体管。 类似地，第二柱状区域是N阱，并且具有四个垂直对准的P型材料的有源区。 每个这样的有源区形成两个PMOS晶体管。 第三列有两个双极晶体管，每个具有垂直对齐的集电极，基极和发射极区。 所得到的BiCMOS逻辑阵列允许宏单元的灵活位置，这导致所得到的集成电路的紧凑实现。

公开(公告)号：EP0351896A3

公开(公告)日：1991-02-27

申请号：EP89200837.6

申请日：1989-04-03

申请人： LSI LOGIC CORPORATION

发明人： Wong, Anthony Y. ,  Wong, Daniel ,  Chan, Steven S.

IPC分类号： H01L27/118 ,  H01L27/06

CPC分类号： H01L27/11896

摘要： An integrated circuit logic array is fabricated using a BiCMOS process so that it includes an optimum number of bipolar drivers. This is accomplished by means of a chip architecture having three regions: the array core is all CMOS logic gates; surrounding the core is a BiCMOS region; at the periphery of the array are simple bipolar and CMOS devices for I/O purposes. The chip can be fabricated to use these regions to create circuit paths of varying complexity, depending on the application. In a second embodiment, the array consists of cells each containing one bipolar device and several contiguous CMOS gates.

公开(公告)号：EP0351896A2

公开(公告)日：1990-01-24

申请号：EP89200837.6

申请日：1989-04-03

申请人： LSI LOGIC CORPORATION

发明人： Wong, Anthony Y. ,  Wong, Daniel ,  Chan, Steven S.

IPC分类号： H01L27/118 ,  H01L27/06

CPC分类号： H01L27/11896

摘要： An integrated circuit logic array is fabricated using a BiCMOS process so that it includes an optimum number of bipolar drivers. This is accomplished by means of a chip architecture having three regions: the array core is all CMOS logic gates; surrounding the core is a BiCMOS region; at the periphery of the array are simple bipolar and CMOS devices for I/O purposes. The chip can be fabricated to use these regions to create circuit paths of varying complexity, depending on the application. In a second embodiment, the array consists of cells each containing one bipolar device and several contiguous CMOS gates.

摘要翻译： 使用BiCMOS工艺制造集成电路逻辑阵列，使其包含最佳数量的双极驱动器。 这通过具有三个区域的芯片架构来实现：阵列核心是所有CMOS逻辑门; 围绕核心是BiCMOS地区; 在阵列的外围是用于I / O目的的简单的双极和CMOS器件。 根据应用，芯片可以被制造成使用这些区域来创建不同复杂度的电路路径。 在第二实施例中，阵列由每个包含一个双极器件和几个连续的CMOS栅极的单元组成。

公开(公告)号：EP0457150A3

公开(公告)日：1992-06-17

申请号：EP91107314.6

申请日：1991-05-06

申请人： LSI LOGIC CORPORATION

发明人： Wong, Anthony Y. ,  Tam, Anna ,  Wong, Daniel

IPC分类号： H01L27/118 ,  H01L27/02

CPC分类号： H01L27/11896

摘要： A repeating cell structure in a semiconductor substrate for a BiCMOS logic gate array. The cell structure has three regions shaped as columns. The first columnar region is a P-well and has four vertically aligned active areas of N-type material formed within the columnar region. Each of the active areas has two gate electrodes to form two NMOS transistors. Similarly the second columnar region is a N-well and has four vertically aligned active areas of P-type material. Each such active region forms two PMOS transistors. The third column has two bipolar transistors, each with collector, base and emitter regions vertically aligned. The resulting BiCMOS logic array permits a flexible location of macrocells, which results in a compact implementation of the resulting integrated circuit.

公开(公告)号：EP0583881A1

公开(公告)日：1994-02-23

申请号：EP93305570.9

申请日：1993-07-15

申请人： LSI LOGIC CORPORATION

发明人： Wong, Anthony Y. ,  Chan, Eric ,  Cheung, Brian ,  Wong, Daniel

IPC分类号： H03K5/15

CPC分类号： H03K5/151

摘要： A CMOS driver circuit which differentially drives a pair of transmission (11,12) lines at a first terminal in response to a signal on the CMOS driver circuit's input terminal (10) for reception of said signal at a second terminal is provided. The driver circuit has two pairs of drive transistors (41,43;42,44). Each drive transistor has first and second source/drains and a gate. Each drive transistor pair is connected to one of said transmission line pair (11,12), and has a NMOS transistor (41,42) and a PMOS transistor (43,44).

摘要翻译： 提供了CMOS驱动器电路，其响应于在CMOS驱动器电路的输入端子（10）上的信号在第一端子差分地驱动一对传输（11,12）线，以在第二端子处接收所述信号。 驱动电路具有两对驱动晶​​体管（41,43; 42,44）。 每个驱动晶体管具有第一和第二源极/漏极和栅极。 每个驱动晶体管对连接到所述传输线对（11,12）中的一个，并且具有NMOS晶体管（41,42）和PMOS晶体管（43,44）。