公开(公告)号：EP0181047A3

公开(公告)日：1988-01-13

申请号：EP85201805

申请日：1985-11-07

申请人： LSI LOGIC CORPORATION

发明人： Chan, Steven S.

IPC分类号： H03K05/13

CPC分类号： H03K19/00323 ,  H03K5/131 ,  H03K2005/00097 ,  H03K2005/00247

摘要： A circuit (40) constructed in accordance with this invention includes a ring oscillator (25) to provide a signal which is dependent on the propagation delays of the inverters (33, 34, 35) comprising the ring oscillator, therefore the frequency of the ring oscillator is inversely dependent upon the propagation delays of the inverter comprising the ring oscillator. Means (37) are provided to determine the propagation delay introduced by the components in the ring oscillator by measuring the frequency of the output signal produced by the ring oscillator which provides a signal to a multiplexer (36) which selects among a number of present delay components (26) those components which are necessary to ensure that the propagation delay caused by the circuitry (not shown) connected to the input lead (21) of the circuit constructed in accordance with this invention plus the propagation delay introduced by the selectable delay elements is nearly a constant propagation delay.

公开(公告)号：EP0181047A2

公开(公告)日：1986-05-14

申请号：EP85201805.0

申请日：1985-11-07

申请人： LSI LOGIC CORPORATION

发明人： Chan, Steven S.

IPC分类号： H03K5/13

CPC分类号： H03K19/00323 ,  H03K5/131 ,  H03K2005/00097 ,  H03K2005/00247

摘要： A circuit (40) constructed in accordance with this invention includes a ring oscillator (25) to provide a signal which is dependent on the propagation delays of the inverters (33, 34, 35) comprising the ring oscillator, therefore the frequency of the ring oscillator is inversely dependent upon the propagation delays of the inverter comprising the ring oscillator. Means (37) are provided to determine the propagation delay introduced by the components in the ring oscillator by measuring the frequency of the output signal produced by the ring oscillator which provides a signal to a multiplexer (36) which selects among a number of present delay components (26) those components which are necessary to ensure that the propagation delay caused by the circuitry (not shown) connected to the input lead (21) of the circuit constructed in accordance with this invention plus the propagation delay introduced by the selectable delay elements is nearly a constant propagation delay.

公开(公告)号：EP0181047B1

公开(公告)日：1992-09-16

申请号：EP85201805.0

申请日：1985-11-07

申请人： LSI LOGIC CORPORATION

发明人： Chan, Steven S.

IPC分类号： H03K5/13

CPC分类号： H03K19/00323 ,  H03K5/131 ,  H03K2005/00097 ,  H03K2005/00247

公开(公告)号：EP0351896A3

公开(公告)日：1991-02-27

申请号：EP89200837.6

申请日：1989-04-03

申请人： LSI LOGIC CORPORATION

发明人： Wong, Anthony Y. ,  Wong, Daniel ,  Chan, Steven S.

IPC分类号： H01L27/118 ,  H01L27/06

CPC分类号： H01L27/11896

摘要： An integrated circuit logic array is fabricated using a BiCMOS process so that it includes an optimum number of bipolar drivers. This is accomplished by means of a chip architecture having three regions: the array core is all CMOS logic gates; surrounding the core is a BiCMOS region; at the periphery of the array are simple bipolar and CMOS devices for I/O purposes. The chip can be fabricated to use these regions to create circuit paths of varying complexity, depending on the application. In a second embodiment, the array consists of cells each containing one bipolar device and several contiguous CMOS gates.

公开(公告)号：EP0351896A2

公开(公告)日：1990-01-24

申请号：EP89200837.6

申请日：1989-04-03

申请人： LSI LOGIC CORPORATION

发明人： Wong, Anthony Y. ,  Wong, Daniel ,  Chan, Steven S.

IPC分类号： H01L27/118 ,  H01L27/06

CPC分类号： H01L27/11896

摘要： An integrated circuit logic array is fabricated using a BiCMOS process so that it includes an optimum number of bipolar drivers. This is accomplished by means of a chip architecture having three regions: the array core is all CMOS logic gates; surrounding the core is a BiCMOS region; at the periphery of the array are simple bipolar and CMOS devices for I/O purposes. The chip can be fabricated to use these regions to create circuit paths of varying complexity, depending on the application. In a second embodiment, the array consists of cells each containing one bipolar device and several contiguous CMOS gates.

摘要翻译： 使用BiCMOS工艺制造集成电路逻辑阵列，使其包含最佳数量的双极驱动器。 这通过具有三个区域的芯片架构来实现：阵列核心是所有CMOS逻辑门; 围绕核心是BiCMOS地区; 在阵列的外围是用于I / O目的的简单的双极和CMOS器件。 根据应用，芯片可以被制造成使用这些区域来创建不同复杂度的电路路径。 在第二实施例中，阵列由每个包含一个双极器件和几个连续的CMOS栅极的单元组成。