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    Complex-admittance digital-to-analog converter
    1.
    发明公开
    Complex-admittance digital-to-analog converter 有权
    Digital-Analog-Umsetzerfürkomplexe Leitwerte

    公开(公告)号：EP2246985A1

    公开(公告)日：2010-11-03

    申请号：EP10004454.4

    申请日：2010-04-27

    申请人： Linear Technology Corporation

    发明人： Thomas, Andrew Joseph ,  Sousa, Joseph Luis

    IPC分类号： H03M1/80 ,  H03M1/06

    CPC分类号： H03M1/80 ,  H03M1/06

    摘要： A circuit includes a digital-to-analog converter configured to produce an analog output signal (1) proportional to a reference signal and (2) as a function of a digital input signal. The converter comprises a plurality of non-trivially complex admittances configured so that each non-trivially complex admittance can be selectively switched as a function of the digital input signal so as to be coupled between a reference terminal configured to receive a reference signal and an output terminal. The method comprises selectively switching non-trivially complex admittances as a function of the digital signal between a reference terminal and an output terminal.

    摘要翻译： 电路包括被配置为产生与参考信号成比例的模拟输出信号（1）和（2）作为数字输入信号的函数的数模转换器。 转换器包括多个非常复杂的导纳，其被配置为使得可以根据数字输入信号选择性地切换每个非平凡复杂的导纳，以便耦合在被配置为接收参考信号的参考端和输出 终奌站。 该方法包括根据参考端和输出端之间的数字信号选择性地切换非常复杂的导纳。

    SUPPRESSING DIELECTRIC ABSORPTION EFFECTS IN SAMPLE-AND-HOLD SYSTEMS
    2.
    发明公开
    SUPPRESSING DIELECTRIC ABSORPTION EFFECTS IN SAMPLE-AND-HOLD SYSTEMS 审中-公开
    ABTAST-HALTE-SYSTEMEN的UNTERDRÜCKUNGDIELEKTRISCHER ABSORPTIONSEFFEKTE

    公开(公告)号：EP2933800A1

    公开(公告)日：2015-10-21

    申请号：EP15001050.2

    申请日：2015-04-13

    申请人： Linear Technology Corporation

    发明人： Thomas, Andrew Joseph

    IPC分类号： G11C27/02

    摘要： Sample-and-hold (S/H) circuitry operating in track and hold phases and having a first S/H circuit with a first hold capacitor at which a first voltage value is maintained in the hold phase, and a dielectric absorption (DA)- suppressing circuit connectable to the first hold capacitor for operating the S/H circuitry in an additional phase after completing the hold phase and before entering the track phase. The DA-suppressing circuit is configured to supply the first hold capacitor, during an operation in the additional phase, with a second voltage value that is negatively correlated with the first voltage value.

    摘要翻译： 采样和保持（S / H）电路工作在跟踪和保持相位，并且具有第一S / H电路与第一保持电容器，第一电压值保持在保持相位中，并且电介质吸收（DA） - 可以连接到第一保持电容器的抑制电路，用于在完成保持阶段之后和在进入轨道相位之前以附加相位操作S / H电路。 DA抑制电路被配置为在附加相中的操作期间向与第一电压值负相关的第二电压值提供第一保持电容。