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公开(公告)号：EP2326988B1
公开(公告)日：2018-11-07
申请号：EP09812368.0
申请日：2009-09-08
申请人： Luxtera, Inc.
发明人： PINGUET, Thierry , GLOECKNER, Steffen , DE DOBBELAERE, Peter , ABDALLA, Sherif , KUCHARSKI, Daniel , MASINI, Gianlorenzo , YOKOYAMA, Kosei , GUCKENBERGER, John , MEKIS, Attila
IPC分类号： G02F3/00 , H04L27/144 , H01L21/84 , H01L27/12
CPC分类号： H04B10/2575 , H01L21/84 , H01L27/1203 , H04B10/40
摘要： Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.
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公开(公告)号：EP3612876A1
公开(公告)日：2020-02-26
申请号：EP18786974.8
申请日：2018-04-19
申请人： Luxtera, Inc.
发明人： BRUCK, Roman , MEKIS, Attila
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公开(公告)号：EP3612873A1
公开(公告)日：2020-02-26
申请号：EP18788076.0
申请日：2018-04-19
申请人： Luxtera, Inc.
发明人： BRUCK, Roman , MEKIS, Attila
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公开(公告)号：EP3635457A1
公开(公告)日：2020-04-15
申请号：EP18813856.4
申请日：2018-06-07
申请人： Luxtera, Inc.
发明人： HON, Kam-Yan , SAHNI, Subal , MASINI, Gianlorenzo , MEKIS, Attila
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公开(公告)号：EP3534209A1
公开(公告)日：2019-09-04
申请号：EP18204690.4
申请日：2009-09-08
申请人： Luxtera, Inc.
发明人： PINGUET, Thierry , GLOECKNER, Steffen , DE DOBBELAERE, Peter , ABDALLA, Sherif , KUCHARSKI, Daniel , MASINI, Gianlorenzo , YOKOYAMA, Kosei , GUCKENBERGER, John , MEKIS, Attila
IPC分类号： G02F3/00 , H04L27/144 , H01L21/84 , H01L27/12 , H01L25/065 , H01L25/16 , H04B10/40
摘要： Monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-msulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.
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公开(公告)号：EP3351983A1
公开(公告)日：2018-07-25
申请号：EP18157074.8
申请日：2013-07-09
申请人： Luxtera, Inc.
发明人： MEKIS, Attila , VERSLEGERS, Lieven
CPC分类号： G02B6/26 , G02B5/1861 , G02B6/124 , G02B6/126 , G02B6/30 , G02B6/34 , G02B6/4214 , G02B2006/12107 , G02B2006/12147 , G02B2006/1215
摘要： Methods and systems for grating couplers incorporating perturbed waveguides are disclosed and may include in a semiconductor photonics die, communicating optical signals into and/or out of the die utilizing a grating coupler on the die, where the grating coupler comprises perturbed waveguides. The perturbed waveguides may comprise a variable width along their length. The grating coupler may comprise a single polarization grating coupler comprising perturbed waveguides and a non-perturbed grating. The grating coupler may comprise a polarization splitting grating coupler (PSGC) that includes two sets of perturbed waveguides at a non-zero angle, or a plurality of non-linear rows of discrete shapes. The PSGC may comprise discrete scatterers at an intersection of the sets of perturbed waveguides. The grating couplers may be etched in a silicon layer on the semiconductor photonics die or deposited on the semiconductor photonics die. The grating coupler may comprise individual scatterers between the perturbed waveguides.
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8.发明公开
公开(公告)号：EP2326988A1
公开(公告)日：2011-06-01
申请号：EP09812368.0
申请日：2009-09-08
申请人： Luxtera, Inc.
发明人： PINGUET, Thierry , GLOECKNER, Steffen , DE DOBBELAERE, Peter , ABDALLA, Sherif , KUCHARSKI, Daniel , MASINI, Gianlorenzo , YOKOYAMA, Kosei , GUCKENBERGER, John , MEKIS, Attila
IPC分类号： G02F3/00 , H04L27/144
CPC分类号： H04B10/2575 , H01L21/84 , H01L27/1203 , H04B10/40
摘要： Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.
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