公开(公告)号：EP1116324A4

公开(公告)日：2005-01-26

申请号：EP99946680

申请日：1999-08-25

申请人： MAXIM INTEGRATED PRODUCTS ,  HISYS GMBH

发明人： FILIP JAN

IPC分类号： H03F3/45 ,  H03F1/30 ,  H03F1/32 ,  H03F1/34

CPC分类号： H03F1/3211

摘要： Disclosed is a differential amplifier including an emitter follower pair (Q1, Q2), a first differential pair (Q3, Q4), and a main differential amplifier (Q5, Q6). The emitter follower pair is operative to receive an input differential voltage signal for shifting the input differential voltage signal to develop a shifted differential voltage signal. The first differential pair is configured to feed a first differential current inversely to the emitter follower pair so that a transconductance of the emitter follower pair changes inversely to compensate for a change in a transconductance of the first differential pair. The main differential amplifier is coupled to receive the shifted differential voltage signal and is configured to amplify the shifted differential voltage signal to generate an output voltage signal.

公开(公告)号：EP1110319A4

公开(公告)日：2001-10-17

申请号：EP99945223

申请日：1999-08-26

申请人： MAXIM INTEGRATED PRODUCTS ,  HISYS GMBH

发明人： FILIP JAN

IPC分类号： H03K19/086 ,  H03F1/30 ,  H03K17/14 ,  H03K17/60 ,  H03K19/003

CPC分类号： H03K19/00376

摘要： Disclosed is a circuit for compensating variations in an ECL circuit (200). The compensation circuit (210) is coupled to the differential pair (Q1/Q2) and the output stage (Q3/Q4) and is operative to develop a compensating voltage drop in the differential pair so as to compensate the DC output voltage level against temperature variations.

摘要翻译： 公开了一种用于补偿ECL电路（200）中的变化的电路。 补偿电路（210）耦合到差分对（Q1 / Q2）和输出级（Q3 / Q4）并且可操作用于在差分对中产生补偿电压降以便补偿DC输出电压电平对温度 变化。

公开(公告)号：EP1116323A4

公开(公告)日：2004-09-29

申请号：EP99946679

申请日：1999-08-25

申请人： MAXIM INTEGRATED PRODUCTS ,  HISYS GMBH

发明人： FILIP JAN

IPC分类号： H03D13/00 ,  H03L7/087 ,  H03L7/095 ,  H03L7/10 ,  H04L7/033 ,  H03D3/24 ,  H03D1/00 ,  H03D3/00 ,  H03D3/02 ,  H03D3/18

CPC分类号： H03L7/087 ,  H03D13/003 ,  H03L7/095 ,  H03L7/10

摘要： Circuit and method for generating a signal for use in locking a second signal on a first signal. The first and second signals have an associated frequency. A first beat note signal (PD1) and a second beat note signal (PD2) are generated from the first and second signals, respectively, when the frequencies of the first and second signals are not equal. The circuit includes a first and second flip-flop and detector circuitry. The first flip-flop (502) is configured to receive the first and second beat note signals for generating a first state signal (S0). The first flip-flop (502) generates the first state signal (S0) by sampling the second beat note signal (PD1) at a first periodic interval of the first beat note signal. The second flip-flop (504) is configured to receive the first and second beat note signals for generating a second state signal (S1). The second flip-flop (504) generates the second state signal (S1) by sampling the second beat note signal at a second periodic interval of the first beat note signal (PD1). The detector circuitry (506, 508) is coupled to receive the first and second state signals from the first and second flip-flops for detecting a polarity of the frequency difference between the first and second signals. The polarity of the frequency difference is defined in a tri-state having a positive state, a negative state, and a zero state.