公开(公告)号：EP0529005A4

公开(公告)日：1994-01-19

申请号：EP91918435

申请日：1991-04-03

申请人： MICRO TECHNOLOGY, INC.

发明人： HENSON, LARRY, P. ,  GAJJAR, KUMAR ,  IDLEMAN, THOMAS, E.

IPC分类号： G06F13/36 ,  G06F13/374 ,  G06F13/18

CPC分类号： G06F13/374 ,  G06F13/36

摘要： The present invention provides a method and apparatus for dynamically modifying the priority of access to a bus (16), where the bus (16) has control and arbitration functions distributed among the devices (20) coupled to the bus (16), with each device (20) having a fixed priority level. Access to the bus by particular devices is selectively inhibited, preventing them from asserting their fixed priority level. In a preferred embodiment, the present invention provides control over the reselection of a SCSI bus (16) by a plurality of SCSI devices (20) coupled to the bus (16) by providing a pseudo busy signal to SCSI devices (20) from which reselection is not desired. In this fashion, an initiator may issue a plurality of commands to the SCSI devices (20) and control the order in which the devices (20) will be serviced when ready.

摘要翻译： 本发明提供了一种用于动态修改对总线（16）的访问优先权的方法和设备，其中总线（16）具有分布在耦合到总线（16）的设备（20）之间的控制和仲裁功能，每个 设备（20）具有固定的优先级。 有选择地禁止特定设备访问总线，从而阻止它们维持固定的优先级。 在一个优选实施例中，本发明通过向SCSI设备（20）提供伪忙信号来提供对耦合到总线（16）的多个SCSI设备（20）重新选择SCSI总线（16）的控制， 重选不是所希望的。 以这种方式，启动器可以向SCSI设备（20）发出多个命令并且在准备好时控制设备（20）将被服务的顺序。

公开(公告)号：EP0532514A4

公开(公告)日：1993-10-06

申请号：EP91908123

申请日：1991-04-03

申请人： MICRO TECHNOLOGY, INC.

发明人： HENSON, LARRY, P. ,  GAJJAR, KUMAR ,  POWERS, DAVID, T. ,  IDLEMAN, THOMAS, E.

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G11B20/18 ,  H04J15/00

CPC分类号： G06F11/10 ,  G06F11/0757 ,  G06F11/1076 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/201 ,  G06F11/2089 ,  G06F11/2094 ,  G06F2211/1057 ,  G11B20/1833

摘要： A mass memory system for digital computers is disclosed. The system has a plurality of disk drives (250-255) coupled to a plurality of small buffers (240-245). An Error Correction Controller (260 and 270) is coupled to a plurality of X-bar switches (210-215), the X-bar switches being connected between each disk drive and its buffers. Data is read from and written to the disk drives in parallel and error correction is also performed in parallel. The X-bar switches are used to couple and decouple functional and nonfunctional disk drives to the system as necessary. Likewise, the buffers can be disconnected from the system should they fail. The parallel architecture, combined with a Reed-Solomon error detection and correction scheme and X-bar switches allows the system to tolerate and correct any two failed drives, allowing for high fault-tolerance operation.