VIRTUAL ADDRESS TABLE
    4.
    发明公开

    公开(公告)号:EP3152665A4

    公开(公告)日:2018-01-24

    申请号:EP15803929

    申请日:2015-05-29

    IPC分类号: G06F12/02 G06F12/06

    摘要: The present disclosure includes apparatuses and methods related to virtual address tables. An example method comprises generating an object file that comprises: an instruction comprising a number of arguments; and an address table comprising a number of indexed address elements. Each one of the number of indexed address elements can correspond to a virtual address of a respective one of the number of arguments, wherein the address table can serves as a target for the number of arguments. The method can include storing the object file in a memory.

    DIVISION OPERATIONS FOR MEMORY
    6.
    发明公开
    DIVISION OPERATIONS FOR MEMORY 审中-公开
    DIVISIONSOPERATIONENFÜRSPEICHER

    公开(公告)号:EP3066665A4

    公开(公告)日:2017-07-05

    申请号:EP14860497

    申请日:2014-11-04

    发明人: WHEELER KYLE B

    IPC分类号: G11C8/06 G11C7/10

    摘要: Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first address space comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space stores a dividend value. A second address space comprises a second number of memory cells coupled to the sense line and to a second number of select lines wherein the second address space stores a divisor value. A third address space comprises a third number of memory cells coupled to the sense line and to a third number of select lines wherein the third address space stores a remainder value. Sensing circuitry can be configured to receive the dividend value and the divisor value, divide the dividend value by the divisor value, and store a remainder result in the third number of memory cells.

    摘要翻译: 本公开的示例提供了用于在存储器中执行划分操作的设备和方法。 示例装置包括:第一地址空间,包括耦合到感测线的第一数量的存储器单元和第一数量的选择线,其中第一地址空间存储被除数。 第二地址空间包括耦合到感测线的第二数量的存储器单元和第二数量的选择线,其中第二地址空间存储除数值。 第三地址空间包括耦合到感测线和第三数量的选择线的第三数量的存储器单元,其中第三地址空间存储余数值。 感测电路可以被配置为接收除数值和除数值,将除数值除以除数值,并将余数结果存储在第三数目的存储器单元中。