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公开(公告)号：EP0877381A3
公开(公告)日：1999-07-07
申请号：EP98201556.2
申请日：1992-04-16
发明人： Dosaka, Katsumi, c/o Mitsubishi Denki K.K. LSI , Kumanoya, Masaki, c/o Mitsubishi Denki K.K. LSI , Yamazaki, Akira, c/o Mitsubishi Denki K.K. LSI , Iwamoto, Hisashi, c/o Mitsubishi Denki K.K. LSI , Konishi, Yasuhiro, c/o Mitsubishi Denki K.K. LSI , Hayano, Kouji, Mitsubishi Denki KK. Kitaitami Sei. , Abe, Hideaki, Mitsubishi Denki KK. Kitaitami Sei. , Himukashi, Katsumitsu, Mitsubishi Elec.Eng.Co.Ltd. , Ishizuka, Yasuhiro, Mitsubishi Elec.Eng.Co.Ltd. , Saiki, Tsukasa, Mitsubishi Elec. Eng. Co. Ltd.
IPC分类号： G11C11/00 , G11C11/418 , G11C11/419
CPC分类号： G11C8/00 , G06F12/0893 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02D10/13
摘要： A semiconductor memory device includes a DRAM (100), an SRAM (200) and a bi-direction transfer gate circuit (210) provided between SRAM (200) and DRAM (100). SRAM array (201; 560) includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer (255). The semiconductor memory device further includes an additional function control circuit (229) for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths (GIL) and (LIL) and data reading paths (LOL) and (GOL) are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.
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公开(公告)号：EP0877382A2
公开(公告)日：1998-11-11
申请号：EP98201557.0
申请日：1992-04-16
发明人： Dosaka, Katsumi, c/o Mitsushiki Denki K.K. LSI , Kumanoya, Masaki, c/o Mitsushiki Denki K.K. LSI , Yamazaki, Akira, c/O Mitsubishi Denki K.K. LSI , Iwamoto, Hisashi, c/o Mitsubishi Denki K.K. LSI , Konishi, Yasuhiro, c/o Mitsubishi Denki K.K. LSI , Hayano, Kouji, c/o Mitsubishi Denki K.K. , Abe, Hideaki, c/o Mitsubishi Denki K.K. , Himukashi, Katsumitsu, c/o Mitsubishi E. E. Co.Ltd , Ishizuka, Yasuhiro, c/o Mitsubishi E. E. Co.Ltd , Saiki, Tsukasa, c/o Mitsubishi E. E. Co.Ltd
IPC分类号： G11C11/00 , G11C11/418 , G11C11/419
CPC分类号： G11C8/00 , G06F12/0893 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02D10/13
摘要： A semiconductor memory device includes a DRAM (100), an SRAM (200) and a bi-direction transfer gate circuit (210) provided between SRAM (200) and DRAM (100). SRAM array (201; 560) includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer (255). The semiconductor memory device further includes an additional function control circuit (229) for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths (GIL) and (LIL) and data reading paths (LOL) and (GOL) are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.
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公开(公告)号：EP0877382B1
公开(公告)日：2002-03-27
申请号：EP98201557.0
申请日：1992-04-16
发明人： Dosaka, Katsumi, c/o Mitsushiki Denki K.K. LSI , Kumanoya, Masaki, c/o Mitsushiki Denki K.K. LSI , Yamazaki, Akira, c/O Mitsubishi Denki K.K. LSI , Iwamoto, Hisashi, c/o Mitsubishi Denki K.K. LSI , Konishi, Yasuhiro, c/o Mitsubishi Denki K.K. LSI , Hayano, Kouji, c/o Mitsubishi Denki K.K. , Abe, Hideaki, c/o Mitsubishi Denki K.K. , Himukashi, Katsumitsu, c/o Mitsubishi E. E. Co.Ltd , Ishizuka, Yasuhiro, c/o Mitsubishi E. E. Co.Ltd , Saiki, Tsukasa, c/o Mitsubishi E. E. Co.Ltd
IPC分类号： G11C11/00 , G11C11/418 , G11C11/419 , G11C8/00
CPC分类号： G11C8/00 , G06F12/0893 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02D10/13
摘要： A semiconductor memory device includes a DRAM (100), an SRAM (200) and a bi-direction transfer gate circuit (210) provided between SRAM (200) and DRAM (100). SRAM array (201; 560) includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer (255). The semiconductor memory device further includes an additional function control circuit (229) for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths (GIL) and (LIL) and data reading paths (LOL) and (GOL) are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.
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公开(公告)号：EP0877382A3
公开(公告)日：1999-07-07
申请号：EP98201557.0
申请日：1992-04-16
发明人： Dosaka, Katsumi, c/o Mitsushiki Denki K.K. LSI , Kumanoya, Masaki, c/o Mitsushiki Denki K.K. LSI , Yamazaki, Akira, c/O Mitsubishi Denki K.K. LSI , Iwamoto, Hisashi, c/o Mitsubishi Denki K.K. LSI , Konishi, Yasuhiro, c/o Mitsubishi Denki K.K. LSI , Hayano, Kouji, c/o Mitsubishi Denki K.K. , Abe, Hideaki, c/o Mitsubishi Denki K.K. , Himukashi, Katsumitsu, c/o Mitsubishi E. E. Co.Ltd , Ishizuka, Yasuhiro, c/o Mitsubishi E. E. Co.Ltd , Saiki, Tsukasa, c/o Mitsubishi E. E. Co.Ltd
IPC分类号： G11C11/00 , G11C11/418 , G11C11/419
CPC分类号： G11C8/00 , G06F12/0893 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02D10/13
摘要： A semiconductor memory device includes a DRAM (100), an SRAM (200) and a bi-direction transfer gate circuit (210) provided between SRAM (200) and DRAM (100). SRAM array (201; 560) includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer (255). The semiconductor memory device further includes an additional function control circuit (229) for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths (GIL) and (LIL) and data reading paths (LOL) and (GOL) are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.
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公开(公告)号：EP0877381A2
公开(公告)日：1998-11-11
申请号：EP98201556.2
申请日：1992-04-16
发明人： Dosaka, Katsumi, c/o Mitsubishi Denki K.K. LSI , Kumanoya, Masaki, c/o Mitsubishi Denki K.K. LSI , Yamazaki, Akira, c/o Mitsubishi Denki K.K. LSI , Iwamoto, Hisashi, c/o Mitsubishi Denki K.K. LSI , Konishi, Yasuhiro, c/o Mitsubishi Denki K.K. LSI , Hayano, Kouji, Mitsubishi Denki KK. Kitaitami Sei. , Abe, Hideaki, Mitsubishi Denki KK. Kitaitami Sei. , Himukashi, Katsumitsu, Mitsubishi Elec.Eng.Co.Ltd. , Ishizuka, Yasuhiro, Mitsubishi Elec.Eng.Co.Ltd. , Saiki, Tsukasa, Mitsubishi Elec. Eng. Co. Ltd.
IPC分类号： G11C11/00 , G11C11/418 , G11C11/419
CPC分类号： G11C8/00 , G06F12/0893 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02D10/13
摘要： A semiconductor memory device includes a DRAM (100), an SRAM (200) and a bi-direction transfer gate circuit (210) provided between SRAM (200) and DRAM (100). SRAM array (201; 560) includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer (255). The semiconductor memory device further includes an additional function control circuit (229) for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths (GIL) and (LIL) and data reading paths (LOL) and (GOL) are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.
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公开(公告)号：EP0817198B1
公开(公告)日：2000-03-15
申请号：EP97201598.6
申请日：1992-04-16
发明人： Dosaka, Katsumi, c/o Mitsubishi Denki K.K. LSI , Kumanoya, Masaki, c/o Mitsubishi Denki K.K. LSI , Yamazaki, Akira, c/o Mitsubishi Denki K.K. LSI , Iwamoto, Hisashi, c/o Mitsubishi Denki K.K. LSI , Konishi, Yasuhiro, c/o Mitsubishi Denki K.K. LSI , Hayano, Kouji, c/o Mitsubishi Denki K.K. , Abe, Hideaki, c/o Mitsubishi Denki K.K. , Himukashi, Katsumitsu, Mitsubishi El. Eng. Co. Ltd , Ishizuka, Yasuhiro, Mitsubishi El. Eng. Co. Ltd , Saiki, Tsukasa, Mitsubishi El. Eng. Co. Ltd
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00 , G11C8/04 , G11C11/406 , G11C11/419 , G11C5/06 , G06F12/08
CPC分类号： G11C8/00 , G06F12/0893 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02D10/13
摘要： A semiconductor memory device includes a DRAM (100), an SRAM (200) and a bi-direction transfer gate circuit (210) provided between SRAM (200) and DRAM (100). SRAM array (201; 560) includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer (255). The semiconductor memory device further includes an additional function control circuit (229) for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths (GIL) and (LIL) and data reading paths (LOL) and (GOL) are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.
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公开(公告)号：EP0817198A1
公开(公告)日：1998-01-07
申请号：EP97201598.6
申请日：1992-04-16
发明人： Dosaka, Katsumi, c/o Mitsubishi Denki K.K. LSI , Kumanoya, Masaki, c/o Mitsubishi Denki K.K. LSI , Yamazaki, Akira, c/o Mitsubishi Denki K.K. LSI , Iwamoto, Hisashi, c/o Mitsubishi Denki K.K. LSI , Konishi, Yasuhiro, c/o Mitsubishi Denki K.K. LSI , Hayano, Kouji, c/o Mitsubishi Denki K.K. , Abe, Hideaki, c/o Mitsubishi Denki K.K. , Himukashi, Katsumitsu, Mitsubishi El. Eng. Co. Ltd , Ishizuka, Yasuhiro, Mitsubishi El. Eng. Co. Ltd , Saiki, Tsukasa, Mitsubishi El. Eng. Co. Ltd
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00 , G11C8/04 , G11C11/406 , G11C11/419 , G11C5/06 , G06F12/08
CPC分类号： G11C8/00 , G06F12/0893 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02D10/13
摘要： A semiconductor memory device includes a DRAM (100), an SRAM (200) and a bi-direction transfer gate circuit (210) provided between SRAM (200) and DRAM (100). SRAM array (201; 560) includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer (255). The semiconductor memory device further includes an additional function control circuit (229) for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths (GIL) and (LIL) and data reading paths (LOL) and (GOL) are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.
摘要翻译： 半导体存储器件包括设置在SRAM（200）和DRAM（100）之间的DRAM（100），SRAM（200）和双向传输门电路（210）。 SRAM阵列（201; 560）包括多组字线。 每组SRAM阵列中提供每组，每组中的每个字线连接到相关行的不同组的存储单元。 SRAM的地址信号和DRAM的地址信号分别应用于地址缓冲器（255）。 半导体存储器件还包括用于实现突发模式和睡眠模式的附加功能控制电路（229）。 从DRAM到SRAM的数据传输路径以及从SRAM到DRAM的数据传输路径分别设置在双向传输门电路中。 在DRAM阵列中分别提供数据写入路径（GIL）和（LIL）以及数据读取路径（LOL）和（GOL）。 通过上述结构，在睡眠模式中停止缓冲电路的动作，降低功耗。 由于数据写入路径和数据读取路径分别设置在DRAM阵列中，所以可以以非多路复用的方式应用DRAM阵列的地址，从而数据可以从DRAM阵列以高速传输到SRAM阵列，使得能够高 高速运行即使在缓存未命中。
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