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公开(公告)号：EP1461811A1
公开(公告)日：2004-09-29
申请号：EP02781031.6
申请日：2002-12-05
IPC分类号： G11C15/04
摘要： A low power CAM architecture is disclosed. Matchlines of the CAM array are segmented into a pre search portion and a main search portion. After issuing a search command, a pre search operation is conducted on the pre search portion of the matchline. If the result of the pre search is a match, then the main search is subsequently conducted on the main search portion of the matchline. If the result of pre search is a mismatch, then the main-search is disabled, and consequently there is no power dissipation on the main search portion of the matchlines. Pre search and main search operations can be pipelined to maintain high throughput with minimum latency. Power consumption is further reduced by using a matchline sense circuit for detecting a current on the pre search and main search portions of the matchline. Matchlines are decoupled from the sense circuit sense node in order to achieve higher sensing speed and improved sense margins, and dummy matchlines are used to generate timed control signals for latching the output of the matchline sense circuits. The matchlines are initially precharged to a miss condition represented by ground potential and are then undergo accelerated precharge to a preset voltage potential level below VDD to overcome tail-out parasitic current and to minimize the voltage swing of the matchlines to conserve power.
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公开(公告)号：EP2127081B1
公开(公告)日：2012-04-11
申请号：EP08714615.5
申请日：2008-02-15
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0688 , G06F13/1694 , G11C7/1045 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C14/0018 , G11C16/0483 , G11C16/10 , G11C16/28 , G11C16/32 , H03K2005/00247 , Y02D10/14
摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.
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公开(公告)号：EP2127081A1
公开(公告)日：2009-12-02
申请号：EP08714615.5
申请日：2008-02-15
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0688 , G06F13/1694 , G11C7/1045 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C14/0018 , G11C16/0483 , G11C16/10 , G11C16/28 , G11C16/32 , H03K2005/00247 , Y02D10/14
摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.
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公开(公告)号：EP2396885A1
公开(公告)日：2011-12-21
申请号：EP10740862.7
申请日：2010-01-11
CPC分类号： H03K3/012 , H01L2924/0002 , H03K19/0005 , H03K19/00361 , H04L25/0278 , H01L2924/00
摘要： In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.
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公开(公告)号：EP2396885B1
公开(公告)日：2013-11-06
申请号：EP10740862.7
申请日：2010-01-11
IPC分类号： H03K19/00 , H04L25/02 , H03K19/003
CPC分类号： H03K3/012 , H01L2924/0002 , H03K19/0005 , H03K19/00361 , H04L25/0278 , H01L2924/00
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公开(公告)号：EP2443629A1
公开(公告)日：2012-04-25
申请号：EP10777275.8
申请日：2010-05-20
CPC分类号： G11C5/025 , G06F13/1684 , G06F13/4022 , G06F13/4243 , G11C16/04
摘要： A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.
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公开(公告)号：EP1461811B1
公开(公告)日：2006-03-29
申请号：EP02781031.6
申请日：2002-12-05
IPC分类号： G11C15/04
摘要： A low power CAM architecture is disclosed. Matchlines of the CAM array are segmented into a pre search portion and a main search portion. After issuing a search command, a pre search operation is conducted on the pre search portion of the matchline. If the result of the pre search is a match, then the main search is subsequently conducted on the main search portion of the matchline. If the result of pre search is a mismatch, then the main-search is disabled, and consequently there is no power dissipation on the main search portion of the matchlines. Pre search and main search operations can be pipelined to maintain high throughput with minimum latency. Power consumption is further reduced by using a matchline sense circuit for detecting a current on the pre search and main search portions of the matchline. Matchlines are decoupled from the sense circuit sense node in order to achieve higher sensing speed and improved sense margins, and dummy matchlines are used to generate timed control signals for latching the output of the matchline sense circuits. The matchlines are initially precharged to a miss condition represented by ground potential and are then undergo accelerated precharge to a preset voltage potential level below VDD to overcome tail-out parasitic current and to minimize the voltage swing of the matchlines to conserve power.
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