公开(公告)号：EP0817383A3

公开(公告)日：1998-01-28

申请号：EP97114992.7

申请日：1992-09-17

申请人： MOTOROLA, INC.

发明人： Yuan-Hslang, Jennifer ,  Flannagan, Stephen ,  Feng, Taisheng

IPC分类号： H03K19/003 ,  H03K19/0175

CPC分类号： H03K19/017527 ,  H03K19/00346 ,  H03K19/017518

摘要： A regulated BICMOS output buffer (34) improves interfacing to loads such as 3.3 volt integrated circuits. The output buffer (34) provides a first voltage to a base of a pullup transistor (116) in response to a difference between an input voltage and a reference voltage. An emitter of the pullup transistor (116) provides an output signal. A second transistor (102) having characteristics matching those of the pullup transistor (116) receives the first voltage at its base, and provides the input voltage at its emitter. The output buffer (34) changes the first voltage until the voltage at the base of the second transistor (102) equals the reference voltage. Thus, signal reflections on the output signal do not affect the performance of the output buffer. Clamps (99, 120) coupled to the base and emitter of the pullup transistor (116) provide soft clamping according to a square law.

摘要翻译： 受控的BICMOS输出缓冲器（34）改进了与负载（例如3.3伏集成电路）的接口。 响应于输入电压与参考电压之间的差异，输出缓冲器（34）向上拉晶体管（116）的基极提供第一电压。 上拉晶体管（116）的发射极提供输出信号。 具有与上拉晶体管（116）的特性匹配的特性的第二晶体管（102）在其基极处接收第一电压，并在其发射极处提供输入电压。 输出缓冲器（34）改变第一电压直到第二晶体管（102）的基极处的电压等于参考电压。 因此，输出信号的信号反射不会影响输出缓冲器的性能。 耦合到上拉晶体管（116）的基极和发射极的钳位（99,120）根据平方律提供软钳位。

公开(公告)号：EP0559368A2

公开(公告)日：1993-09-08

申请号：EP93301338.5

申请日：1993-02-23

申请人： MOTOROLA, INC.

发明人： Feng, Taisheng ,  Flannagan, Stephen ,  Porter, John David

IPC分类号： G06F11/20

CPC分类号： G11C29/80 ,  G11C29/78 ,  G11C29/808 ,  G11C29/846

摘要： A memory (20) has a plurality of columns of memory cells and has a plurality of redundant columns of memory cells. A comparator (45) detects an access to a defective column. A redundant write generator (31) and write fuses (32) are provided for each write portion (30A, 30B, 30C, and 30D) to replace the defective column with a redundant column by replacing a write global data line (37) with a redundant write global data line (39). Redundant read generators (60 and 61) and read fuses (59) are provided for each read portion (50A, 50B, 50C, and 50D) to replace a defective column by deselecting a read global data line (29) and replacing it with a redundant read global data line (44). The fuses and redundant generators are located close to their global data lines, thus reducing the routing of control signals and improving the access time of redundant columns.

摘要翻译： 存储器（20）具有多列存储器单元并且具有多个存储器单元的冗余列。 比较器（45）检测对缺陷列的访问。 为每个写入部分（30A，30B，30C和30D）提供冗余写入发生器（31）和写保险丝（32），以用冗余列替换缺陷列，通过用写入全局数据线（37）替换 冗余写全局数据线（39）。 为每个读取部分（50A，50B，50C和50D）提供冗余读取发生器（60和61）和读取保险丝（59），以通过取消选择读取的全局数据线（29）来替换有缺陷的列，并用 冗余读取全局数据线（44）。 保险丝和冗余发生器位于其全球数据线附近，从而减少控制信号的路由，并改善冗余列的访问时间。

公开(公告)号：EP0533481A1

公开(公告)日：1993-03-24

申请号：EP92308502.1

申请日：1992-09-17

申请人： MOTOROLA, INC.

发明人： Chiao, Jennifer ,  Flannagan, Stephen ,  Feng, Taisheng

IPC分类号： H03K17/04 ,  H03K19/08

CPC分类号： H03K19/017527 ,  H03K19/00346 ,  H03K19/017518

摘要： A regulated BICMOS output buffer (34) improves interfacing to loads such as 3.3 volt integrated circuits. The output buffer (34) provides a first voltage to a base of a pullup transistor (116) in response to a difference between an input voltage and a reference voltage. An emitter of the pullup transistor (116) provides an output signal. A second transistor (102) having characteristics matching those of the pullup transistor (116) receives the first voltage at its base, and provides the input voltage at its emitter. The output buffer (34) changes the first voltage until the voltage at the base of the second transistor (102) equals the reference voltage. Thus, signal reflections on the output signal do not affect the performance of the output buffer. Clamps (99, 120) coupled to the base and emitter of the pullup transistor (116) provide soft clamping according to a square law.

摘要翻译： 调节的BICMOS输出缓冲器（34）可改善与3.3V集成电路等负载的接口。 响应于输入电压和参考电压之间的差异，输出缓冲器（34）向上拉晶体管（116）的基极提供第一电压。 上拉晶体管（116）的发射极提供输出信号。 具有与上拉晶体管（116）匹配的特性的第二晶体管（102）在其基极处接收第一电压，并在其发射极处提供输入电压。 输出缓冲器（34）改变第一电压，直到第二晶体管（102）的基极处的电压等于参考电压。 因此，输出信号上的信号反射不会影响输出缓冲器的性能。 耦合到上拉晶体管（116）的基极和发射极的钳位（99,120）根据平方律提供软钳位。

公开(公告)号：EP0559368B1

公开(公告)日：1998-05-06

申请号：EP93301338.5

申请日：1993-02-23

申请人： MOTOROLA, INC.

发明人： Feng, Taisheng ,  Flannagan, Stephen ,  Porter, John David

IPC分类号： G06F11/20

CPC分类号： G11C29/80 ,  G11C29/78 ,  G11C29/808 ,  G11C29/846

摘要： A memory (20) has a plurality of columns of memory cells and has a plurality of redundant columns of memory cells. A comparator (45) detects an access to a defective column. A redundant write generator (31) and write fuses (32) are provided for each write portion (30A, 30B, 30C, and 30D) to replace the defective column with a redundant column by replacing a write global data line (37) with a redundant write global data line (39). Redundant read generators (60 and 61) and read fuses (59) are provided for each read portion (50A, 50B, 50C, and 50D) to replace a defective column by deselecting a read global data line (29) and replacing it with a redundant read global data line (44). The fuses and redundant generators are located close to their global data lines, thus reducing the routing of control signals and improving the access time of redundant columns.

公开(公告)号：EP0817384A2

公开(公告)日：1998-01-07

申请号：EP97114993.5

申请日：1992-09-17

申请人： MOTOROLA, INC.

发明人： Flannagan, Stephen

IPC分类号： H03K19/003 ,  H03K19/0175

CPC分类号： H03K19/017527 ,  H03K19/00346 ,  H03K19/017518

摘要： A regulated BICMOS output buffer (34) improves interfacing to loads such as 3.3 volt integrated circuits. The output buffer (34) provides a first voltage to a base of a pullup transistor (116) in response to a difference between an input voltage and a reference voltage. An emitter of the pullup transistor (116) provides an output signal. A second transistor (102) having characteristics matching those of the pullup transistor (116) receives the first voltage at its base, and provides the input voltage at its emitter. The output buffer (34) changes the first voltage until the voltage at the base of the second transistor (102) equals the reference voltage. Thus, signal reflections on the output signal do not affect the performance of the output buffer. Clamps (99, 120) coupled to the base and emitter of the pullup transistor (116) provide soft clamping according to a square law.

公开(公告)号：EP0559368A3

公开(公告)日：1994-04-27

申请号：EP93301338.5

申请日：1993-02-23

申请人： MOTOROLA, INC.

发明人： Feng, Taisheng ,  Flannagan, Stephen ,  Porter, John David

IPC分类号： G06F11/20

CPC分类号： G11C29/80 ,  G11C29/78 ,  G11C29/808 ,  G11C29/846

摘要： A memory (20) has a plurality of columns of memory cells and has a plurality of redundant columns of memory cells. A comparator (45) detects an access to a defective column. A redundant write generator (31) and write fuses (32) are provided for each write portion (30A, 30B, 30C, and 30D) to replace the defective column with a redundant column by replacing a write global data line (37) with a redundant write global data line (39). Redundant read generators (60 and 61) and read fuses (59) are provided for each read portion (50A, 50B, 50C, and 50D) to replace a defective column by deselecting a read global data line (29) and replacing it with a redundant read global data line (44). The fuses and redundant generators are located close to their global data lines, thus reducing the routing of control signals and improving the access time of redundant columns.

摘要翻译： 存储器（20）具有多列存储单元并具有多个存储单元的冗余列。 比较器（45）检测对有缺陷列的访问。 为每个写入部分（30A，30B，30C和30D）提供冗余写入发生器（31）和写入熔丝（32），以通过用写入全局数据线（37）替换写入全局数据线 冗余写入全局数据线（39）。 为每个读取部分（50A，50B，50C和50D）提供冗余读取发生器（60和61）和读取熔丝（59），以通过取消选择读取的全局数据行（29）并用 冗余读取全局数据线（44）。 保险丝和冗余发生器位于其全局数据线附近，从而减少了控制信号的路由并改善了冗余列的访问时间。

公开(公告)号：EP0817384B1

公开(公告)日：2001-01-31

申请号：EP97114993.5

申请日：1992-09-17

申请人： MOTOROLA, INC.

发明人： Flannagan, Stephen

IPC分类号： H03K19/003 ,  H03K19/0175 ,  H03G11/00

CPC分类号： H03K19/017527 ,  H03K19/00346 ,  H03K19/017518

公开(公告)号：EP0533481B1

公开(公告)日：1998-03-04

申请号：EP92308502.1

申请日：1992-09-17

申请人： MOTOROLA, INC.

发明人： Chiao, Jennifer ,  Flannagan, Stephen ,  Feng, Taisheng

IPC分类号： H03K19/0175 ,  H03K17/04 ,  H03K19/08

CPC分类号： H03K19/017527 ,  H03K19/00346 ,  H03K19/017518

公开(公告)号：EP0817384A3

公开(公告)日：1998-01-28

申请号：EP97114993.5

申请日：1992-09-17

申请人： MOTOROLA, INC.

发明人： Flannagan, Stephen

IPC分类号： H03K19/003 ,  H03K19/0175

CPC分类号： H03K19/017527 ,  H03K19/00346 ,  H03K19/017518

摘要： A regulated BICMOS output buffer (34) improves interfacing to loads such as 3.3 volt integrated circuits. The output buffer (34) provides a first voltage to a base of a pullup transistor (116) in response to a difference between an input voltage and a reference voltage. An emitter of the pullup transistor (116) provides an output signal. A second transistor (102) having characteristics matching those of the pullup transistor (116) receives the first voltage at its base, and provides the input voltage at its emitter. The output buffer (34) changes the first voltage until the voltage at the base of the second transistor (102) equals the reference voltage. Thus, signal reflections on the output signal do not affect the performance of the output buffer. Clamps (99, 120) coupled to the base and emitter of the pullup transistor (116) provide soft clamping according to a square law.

摘要翻译： 受控的BICMOS输出缓冲器（34）改进了与负载（例如3.3伏集成电路）的接口。 响应于输入电压与参考电压之间的差异，输出缓冲器（34）向上拉晶体管（116）的基极提供第一电压。 上拉晶体管（116）的发射极提供输出信号。 具有与上拉晶体管（116）的特性匹配的特性的第二晶体管（102）在其基极处接收第一电压，并在其发射极处提供输入电压。 输出缓冲器（34）改变第一电压直到第二晶体管（102）的基极处的电压等于参考电压。 因此，输出信号的信号反射不会影响输出缓冲器的性能。 耦合到上拉晶体管（116）的基极和发射极的钳位（99,120）根据平方律提供软钳位。

公开(公告)号：EP0817383A2

公开(公告)日：1998-01-07

申请号：EP97114992.7

申请日：1992-09-17

申请人： MOTOROLA, INC.

发明人： Yuan-Hslang, Jennifer ,  Flannagan, Stephen ,  Feng, Taisheng

IPC分类号： H03K19/003 ,  H03K19/0175

CPC分类号： H03K19/017527 ,  H03K19/00346 ,  H03K19/017518

摘要： A regulated BICMOS output buffer (34) improves interfacing to loads such as 3.3 volt integrated circuits. The output buffer (34) provides a first voltage to a base of a pullup transistor (116) in response to a difference between an input voltage and a reference voltage. An emitter of the pullup transistor (116) provides an output signal. A second transistor (102) having characteristics matching those of the pullup transistor (116) receives the first voltage at its base, and provides the input voltage at its emitter. The output buffer (34) changes the first voltage until the voltage at the base of the second transistor (102) equals the reference voltage. Thus, signal reflections on the output signal do not affect the performance of the output buffer. Clamps (99, 120) coupled to the base and emitter of the pullup transistor (116) provide soft clamping according to a square law.

摘要翻译： 调节的BICMOS输出缓冲器（34）可改善与3.3V集成电路等负载的接口。 响应于输入电压和参考电压之间的差异，输出缓冲器（34）向上拉晶体管（116）的基极提供第一电压。 上拉晶体管（116）的发射极提供输出信号。 具有与上拉晶体管（116）匹配的特性的第二晶体管（102）在其基极处接收第一电压，并在其发射极处提供输入电压。 输出缓冲器（34）改变第一电压，直到第二晶体管（102）的基极处的电压等于参考电压。 因此，输出信号上的信号反射不会影响输出缓冲器的性能。 耦合到上拉晶体管（116）的基极和发射极的钳位（99,120）根据平方律提供软钳位。