公开(公告)号：EP0717347A2

公开(公告)日：1996-06-19

申请号：EP95119621.1

申请日：1995-12-13

申请人： MOTOROLA, INC.

发明人： Smolansky, Leonid ,  Kowal, Shai ,  Goren, Avner ,  Galanti, David

IPC分类号： G06F5/06

CPC分类号： G06F5/06 ,  G06F9/3879

摘要： An adjustable depth/width FIFO buffer (65) is provided that accommodates variable width data transfers. The FIFO buffer (65) has two sections of read/write registers (73, 75) that are each independently controlled for transferring 16 bit words or 32 bit words without wasting register space in the FIFO buffer (65) when transferring 16 bit words. When the FIFO buffer (65) is narrowed to transfer 16 bit words, the storage space is deepened. This allows maximum use of the FIFO buffer registers (72) when interfacing either 16 bits of parallel data or 32 bits of parallel data. The FIFO buffer (65) is a slave only buffer to a host processor, therefore, the FIFO buffer (65) cannot initiate output of data, keeping the design simple and small.

公开(公告)号：EP0717348A2

公开(公告)日：1996-06-19

申请号：EP95119622.9

申请日：1995-12-13

申请人： MOTOROLA, INC.

发明人： Smolansky, Leonid ,  Kowal, Shai ,  Goren, Avner ,  Galanti, David

IPC分类号： G06F5/06

CPC分类号： H04L49/9057 ,  G06F5/06 ,  G06F9/3879 ,  H04L29/06 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9052

摘要： A method and apparatus are provided for inserting an address at the beginning of a data stream that is being transferred through a FIFO buffer (65). The address is inserted at the beginning of the data stream to prevent the address from being lost. An address decoder (102) is used to identify a range of addresses that can access the FIFO buffer (65). The address may also contain header information for determining the destination of the data stream in a data processing system (20), and also contain information for controlling how the data stream is to be processed in the data processing system (20).

摘要翻译： 提供了用于插入在数据流的开始，以解决被并通过一个FIFO缓冲器（65）传送的方法和装置。 地址插在数据流，以防止地址被丢失的开始。 地址解码器（102）被用来识别一个地址范围确实可以访问FIFO缓冲器（65）。 因此，该地址可以包含用于确定挖掘头信息中的数据处理系统（20）中的数据流的目的地，因此，包含的信息用于控制数据流是如何在所述数据处理系统（20）以进行处理。

公开(公告)号：EP0783148A3

公开(公告)日：1999-08-25

申请号：EP96114708.9

申请日：1996-09-12

申请人： MOTOROLA, INC.

发明人： Smolyansky, Leonid ,  Kowal, Shai ,  Goren, Avner ,  Galanti, David

IPC分类号： G06F1/32

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/325 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

摘要： Power consumption of a modular system (40) coupled by a bus (48) is reduced by separating the module (44) clock into two parts: (i) a low power clock (56) which provides a substantially continuous signal (100) and drives the module access logic (60), and (ii) a high power main clock driver (72) that operates only when the module (44) has detected its own address. When the access logic (60) detects the module address (104), it causes an enable/disable circuit (68) to turn on the main clock driver (72) supplying the module function logic (64), which then reads or writes to the bus (48) or performs other operations according to its internal programming or control signals on the bus (48) or both. When finished, the function logic (64) sends a shut-down signal (120) to the enable/disable circuit (68) to terminate operation of the main clock driver (72). The module returns (44) to its quiescent state until receipt of the next address event (104).

公开(公告)号：EP0814412B1

公开(公告)日：2003-03-12

申请号：EP96109840.7

申请日：1996-06-19

申请人： MOTOROLA, INC.

发明人： Itkin, Yuval ,  Kowal, Shai ,  Rozenshein, Zvi

IPC分类号： G06F15/78

CPC分类号： G06F9/3879 ,  G06F15/7857

公开(公告)号：EP0717347A3

公开(公告)日：1997-06-04

申请号：EP95119621.1

申请日：1995-12-13

申请人： MOTOROLA, INC.

发明人： Smolansky, Leonid ,  Kowal, Shai ,  Goren, Avner ,  Galanti, David

IPC分类号： G06F5/06

CPC分类号： G06F5/06 ,  G06F9/3879

摘要： An adjustable depth/width FIFO buffer (65) is provided that accommodates variable width data transfers. The FIFO buffer (65) has two sections of read/write registers (73, 75) that are each independently controlled for transferring 16 bit words or 32 bit words without wasting register space in the FIFO buffer (65) when transferring 16 bit words. When the FIFO buffer (65) is narrowed to transfer 16 bit words, the storage space is deepened. This allows maximum use of the FIFO buffer registers (72) when interfacing either 16 bits of parallel data or 32 bits of parallel data. The FIFO buffer (65) is a slave only buffer to a host processor, therefore, the FIFO buffer (65) cannot initiate output of data, keeping the design simple and small.

摘要翻译： 提供了一种可调深度/宽度FIFO缓冲器（65）做了容纳可变宽度数据传送。 FIFO缓冲器（65）具有（73，75）做各自unabhängig控制以传递环16位的字或者32位的字，而不在FIFO缓冲器（65）当传递环16位字浪费寄存器空间的读/写寄存器两个部分。 当FIFO缓冲器（65）变窄，以传输16个字时，存储空间被加深。 这允许最大限度利用FIFO缓冲器寄存器（72），当连接的并行数据的任16位或并行数据的32位。 FIFO缓冲器（65）是一个从仅缓冲到主机处理器，因此，FIFO缓冲器（65）不能启动数据的输出，保持设计简单且小的。

公开(公告)号：EP0783148A2

公开(公告)日：1997-07-09

申请号：EP96114708.9

申请日：1996-09-12

申请人： MOTOROLA, INC.

发明人： Smolyansky, Leonid ,  Kowal, Shai ,  Goren, Avner ,  Galanti, David

IPC分类号： G06F1/32

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/325 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

摘要： Power consumption of a modular system (40) coupled by a bus (48) is reduced by separating the module (44) clock into two parts: (i) a low power clock (56) which provides a substantially continuous signal (100) and drives the module access logic (60), and (ii) a high power main clock driver (72) that operates only when the module (44) has detected its own address. When the access logic (60) detects the module address (104), it causes an enable/disable circuit (68) to turn on the main clock driver (72) supplying the module function logic (64), which then reads or writes to the bus (48) or performs other operations according to its internal programming or control signals on the bus (48) or both. When finished, the function logic (64) sends a shut-down signal (120) to the enable/disable circuit (68) to terminate operation of the main clock driver (72). The module returns (44) to its quiescent state until receipt of the next address event (104).

摘要翻译： 通过将模块（44）分为两部分来减少由总线（48）耦合的模块化系统（40）的功耗：（i）提供基本上连续的信号（100）的低功率时钟（56）和 驱动模块访问逻辑（60），以及（ii）仅当模块（44）已经检测到其自己的地址时才操作的高功率主时钟驱动器（72）。 当访问逻辑（60）检测到模块地址（104）时，它使得启用/禁用电路（68）接通提供模块功能逻辑（64）的主时钟驱动器（72），然后读取或写入 总线（48）或根据其总线（48）上的内部编程或控制信号或两者执行其他操作。 完成后，功能逻辑（64）向使能/禁止电路（68）发送关闭信号（120）以终止主时钟驱动器（72）的操作。 模块返回（44）到其静止状态，直到接收到下一个地址事件（104）。

公开(公告)号：EP0717348A3

公开(公告)日：1997-06-04

申请号：EP95119622.9

申请日：1995-12-13

申请人： MOTOROLA, INC.

发明人： Smolansky, Leonid ,  Kowal, Shai ,  Goren, Avner ,  Galanti, David

IPC分类号： G06F5/06

CPC分类号： H04L49/9057 ,  G06F5/06 ,  G06F9/3879 ,  H04L29/06 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9052

摘要： A method and apparatus are provided for inserting an address at the beginning of a data stream that is being transferred through a FIFO buffer (65). The address is inserted at the beginning of the data stream to prevent the address from being lost. An address decoder (102) is used to identify a range of addresses that can access the FIFO buffer (65). The address may also contain header information for determining the destination of the data stream in a data processing system (20), and also contain information for controlling how the data stream is to be processed in the data processing system (20).