公开(公告)号：EP1155499A4

公开(公告)日：2004-08-25

申请号：EP00976887

申请日：2000-11-02

申请人： MOTOROLA INC

发明人： GAILUS PAUL H ,  TURNEY WILLIAM J

IPC分类号： H03F1/02 ,  H03F1/32 ,  H03F1/56 ,  H04L27/36

CPC分类号： H03F1/3247 ,  H03F1/0227 ,  H03F1/565 ,  H03F2200/102 ,  H04L27/368

摘要： A method and apparatus is provided that amplitude modulates a modulated radio frequency (RF) signal (411) by modulating the supply voltage of a power amplifier (410). The method and apparatus further provide an impedance modulator (412) that reduces output signal (415) errors in response to an error signal generated by a feedback circuit (416) that includes a quadrature modulator (506), a limiter (520), a comparator (502), and a quadrature downconverter (510). Intermodulation distortion generated in the feedback circuit (416) by delay mismatches between amplitude and phase feedback paths, and non-linear effects of AM/PM conversion in a limiter (520), are suppressed by placing limiter (520) and quadrature downconverter (510) in a forward path of the overall amplifier loop.

公开(公告)号：EP1751867A4

公开(公告)日：2009-11-18

申请号：EP05725604

申请日：2005-03-14

申请人： MOTOROLA INC

发明人： WILHITE JEFFREY B ,  CHARASKA JOSEPH A ,  GABATO MANUEL P JR ,  GAILUS PAUL H ,  STENGEL ROBERT E

IPC分类号： H03L7/189 ,  H03J7/06 ,  H03K5/00 ,  H03K5/13 ,  H03L7/06 ,  H03L7/081 ,  H03L7/099 ,  H03L7/16

CPC分类号： H03L7/16 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/0812

摘要： A delay-locked loop 300 that includes: an adjustable frequency source ( 320 ) for generating a clock signal ( 322 ) having an adjustable frequency; an adjustment and tap selection controller ( 310 ) for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line ( 330 ) configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit ( 370 ) for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.

公开(公告)号：EP1810397A4

公开(公告)日：2008-11-19

申请号：EP05796136

申请日：2005-09-12

申请人： MOTOROLA INC

发明人： GABATO MANUEL P JR ,  CHARASKA JOSEPH A ,  GAILUS PAUL H

IPC分类号： H03B21/00 ,  H03K5/14 ,  H03L7/081 ,  H03L7/16

CPC分类号： H03L7/0812 ,  H03K5/1504 ,  H03K2005/00032 ,  H03L7/07 ,  H03L7/16

摘要： A DPC (200) that includes: a frequency source (20); a delay-locked loop (220) for receiving a clock signal and generating a plurality of phase-shifted clock signals; a control device (280) having a DPS (282) and a DAC (284) for receiving an input signal identifying a desired frequency for a synthesized signal; a selection circuit (270) for receiving the plurality of phase-shifted clock signals, selecting a sequence of the phase-shifted clock signals and outputting a coarse synthesized signal; a variable delay cell (290) having a first input coupled to the selection circuit to receive the coarse synthesized signal and a second input coupled to the control device for receiving a fine tune adjustment signal to modify the coarse synthesized signal to generate the synthesized signal (292) having substantially the desired frequency. The DPC further includes training apparatus for calibrating the DPC.

公开(公告)号：EP0875094A4

公开(公告)日：2004-05-19

申请号：EP96944303

申请日：1996-12-13

申请人： MOTOROLA INC

发明人： GAILUS PAUL H ,  MCCALLUM KEVIN J

IPC分类号： H03B21/00 ,  H03D7/16 ,  H04B1/04 ,  H04B1/02 ,  G06F7/44 ,  H03B19/00 ,  H04B1/28 ,  H04L27/30

CPC分类号： H03D7/165 ,  H03B21/00 ,  H04B1/04 ,  H04B2001/0491

摘要： An apparatus comprises a current generator (101) having an output. A plurality of mixers (103, 105, and 107) is switchably coupled to the current generator output, such that a first average power output level is provided when a first mixer (103) of the plurality of mixers is engaged and a second average power output level is provided when a second mixer (105) of the plurality of mixers is engaged. The first average power output level and the second average power output level are different.

公开(公告)号：EP1123609A4

公开(公告)日：2003-01-08

申请号：EP99970816

申请日：1999-10-14

申请人： MOTOROLA INC

发明人： MARTIN WILLIAM J ,  TURNEY WILLIAM J ,  GAILUS PAUL H ,  CLARK EDWARD T ,  DOREVITCH JOSHUA E ,  MANSFIELD TERRY K

IPC分类号： H04B1/00 ,  H04B1/28 ,  H04L23/00

CPC分类号： H04B1/005 ,  H04B1/00 ,  H04B1/28

摘要： An integrated sigma-delta radio frequency (RF) receiver subsystem (200) and method utilizes a multi-mode sigma-delta analog-to-digital converter (215) for providing a single and multi-bit output. A programmable decimation network (221) for reducing the frequency of the in-phase and quadrature bit stream and a programmable formatting network (223) are also used for organizing the in-phase and quadrature components from the decimation network (221) for subsequent signal processing. The invention offers a highly integrated digital/analog RF receiver back-end which incorporates integrated filtering and a smart gain control that is compatible for use with other receiver systems and offering superior performance characteristics.