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    Semiconductor IC and method of making the same
    7.
    发明公开
    Semiconductor IC and method of making the same 失效
    Integrierte Halbleiterschaltung und Verfahren zur Herstellung derselben。

    公开(公告)号：EP0093304A1

    公开(公告)日：1983-11-09

    申请号：EP83103726.2

    申请日：1983-04-18

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Takemoto, Toyoki ,  Komeda, Tadao ,  Yamada, Haruyasu ,  Fujita, Tsutomu

    IPC分类号： H01L27/06 ,  H01L27/08 ,  H01L21/82

    CPC分类号： H01L27/0244 ,  H01L21/74 ,  H01L21/761 ,  H01L21/82285 ,  H01L27/0623 ,  H01L27/0826 ,  H01L27/0922 ,  Y10S148/009 ,  Y10S148/151

    摘要： In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p-collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in Figure 9, p-regions (40) and (49) are formed simultaneously with the p-collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting III of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p-region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h FE transistor, high speed vertical npn transistor, cross-over devices, p-channel and/or n-channel MOS transistors can be formed within limited manufacturing steps.

    摘要翻译： 在半导体IC中，通过在n型外延区域中形成例如集电极区域（39），形成具有均匀特性和高击穿电压的垂直pnp或npn晶体管，n阱 形成在p - 集电极区域（39）中的基极区域（41）和形成在n阱基极区域（41）中的p型发射极区域（42）。 此外，例如，p + - 区域（40）和（49）与p - 集电极区域（39）同时形成，并且n区域（53）与n阱同时形成 基极区域（41），从而在不大幅度增加制造步骤的同时形成垂直晶体管，从而构成优异特性的IIL和高电阻器件; 并且以类似的方式，通过将上述同步步骤中形成的p +区域和n区域与形成垂直晶体管，高hFE晶体管，高速垂直npn晶体管同时形成的其它区域组合， 交叉设备，p沟道和/或n沟道MOS晶体管可以在有限的制造步骤内形成。

    Semiconductor integrated circuit
    10.
    发明公开
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：EP0054303A2

    公开(公告)日：1982-06-23

    申请号：EP81110459.5

    申请日：1981-12-15

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Takemoto, Toyoki ,  Yamada, Haruyasu ,  Fujita, Tsutomu ,  Komeda, Tadao

    IPC分类号： H01L27/06

    CPC分类号： H01L27/0233 ,  H01L21/8222 ,  H01L27/0244 ,  H01L27/0647 ,  H01L29/8605 ,  H01L29/93

    摘要： In an integrated circuit comprising an IIL and a high frequency npn bipolar transistor which has a deep p - -type base region 45 for its inverted npn output transistors, circuit elements such as a resistor part R, a capacitor part C, a diode part D and an isolated crossing connection part Cr are provided with deep p - -type regions 54, 54', 65', 71 and 82 which are formed at the same time with the p - -type region 45 in the IIL, and thereby, reliability of the circuit elements as well as characteristic thereof are improved, thereby further improving manufacturing yields.

    摘要翻译： 在包括IIL和高频npn双极晶体管的集成电路中，其具有用于其反相npn输出晶体管的深p型基极区45，诸如电阻器部分R，电容器部分C，二极管部分D 和隔离的交叉连接部分Cr设置有与IIL中的p-型区域45同时形成的深p-型区域54,54'，65'，71和82，从而可靠性 的电路元件及其特性得到改善，从而进一步提高了制造产量。