公开(公告)号：EP3041142A2

公开(公告)日：2016-07-06

申请号：EP15185464.3

申请日：2015-09-16

申请人： MediaTek, Inc

发明人： CHEN, Shang-Pin ,  LI, An-Siou

IPC分类号： H03K19/0185

CPC分类号： H03K19/017509 ,  G11C7/1057 ,  G11C7/1084 ,  H03K19/018507

摘要： A method for performing signal driving control in an electronic device (100, 300) and an associated apparatus (100, 300) are provided. The method includes: generating a first driving control signal (MOD1) and a second driving control signal (MOD2) according to a data signal (DATA), wherein the second driving control signal (MOD2) transits in response to a transition of the data signal (DATA), and the first driving control signal (MOD1) includes a pulse corresponding to the transition of the data signal (DATA); and utilizing a first switching unit to control a first signal path between a first voltage level (LEVEL1, SUP1) and an output terminal (OUT) of an output stage according to the first driving control signal (MOD1), and utilizing a second switching unit to control a second signal path between the first voltage level (LEVEL1, SUP1) and the output terminal (OUT) according to the second driving control signal (MOD2), wherein a first impedance (Z1) of the first signal path is less than a second impedance (Z2) of the second signal path.

摘要翻译： 提供了一种用于在电子设备（100，300）和相关联的设备（100，300）进行信号的驱动控制方法。 该方法包括：响应于所述数据信号的转变产生雅丁第一驱动控制信号（MOD 1）和第二驱动控制信号（MOD 2）的数据信号（DATA），worin第二驱动控制信号（MOD 2）转变 （DATA），并且所述第一驱动控制信号（MOD 1）包括一脉冲对应于数据信号（DATA）的过渡; 与利用一个第一开关单元，用于控制第一电压电平（LEVEL1，SUP1）和输出级雅丁到第一驱动控制信号的输出端（OUT）（MOD 1）之间的第一信号路径，和利用第二开关单元 来控制所述第一电压电平（LEVEL1，SUP1）和雅丁到第二驱动控制信号（MOD 2）worin所述第一信号路径的第一阻抗（Z1）小于所述输出端（OUT）之间的第二信号路径 所述第二信号路径的第二阻抗（Z2）。

公开(公告)号：EP3128516A1

公开(公告)日：2017-02-08

申请号：EP16178385.7

申请日：2016-07-07

申请人： MediaTek Inc.

发明人： LI, An-Siou ,  CHEN, Shang-Pin

IPC分类号： G11C7/10 ,  G11C5/14

CPC分类号： H03K17/687 ,  G11C5/14 ,  G11C7/1057 ,  G11C7/1069 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

摘要： An apparatus (100) for performing signal driving in an electronic device (100) may include a decoupling capacitor and at least one switching unit (SW1, SW2). The decoupling capacitor may have a first terminal and a second terminal, and may be positioned in an output stage within the electronic device (100) and coupled between a first predetermined voltage level and another predetermined voltage level, where the apparatus (100) may perform signal driving with aid of the output stage. In addition, the aforementioned at least one switching unit (SW1, SW2) may be coupled between one terminal of the first and the second terminals of the decoupling capacitor and at least one of the first predetermined voltage level and the other predetermined voltage level, and may be arranged for selectively disabling the decoupling capacitor.

摘要翻译： 用于执行信号驱动到电子设备（100）的装置（100）可以包括去耦电容器和至少一个切换单元（SW1，SW2）。 去耦电容器可以具有第一端子和第二端子，并且可在向电子设备（100）内的输出级被定位和连接第一预定电压电平与另一个预定电压电平，其中，所述设备（100）可以执行之间 信号与所述输出级的辅助驱动。 另外，上述的至少一个开关单元（SW1，SW2）可在第一的一个端子和去耦电容器的第二端子和第一预定电压电平中的至少一个和另一个预定的电压电平之间，以及被耦合 可以布置成用于选择性地禁止所述去耦电容器。

公开(公告)号：EP3041141A2

公开(公告)日：2016-07-06

申请号：EP15195296.7

申请日：2015-11-19

申请人： MediaTek, Inc

发明人： CHIANG, Chen-Feng ,  LI, An-Siou

IPC分类号： H03K19/00 ,  H03K19/003 ,  H03K19/0185

CPC分类号： H03K17/6871 ,  H03K17/08142 ,  H03K17/693 ,  H03K19/0027 ,  H03K19/00384 ,  H03K19/018521

摘要： An I/O driving circuit including a post driver (200, 300, 403, 503, 603), wherein the post driver (200, 300, 403, 503, 603) includes: a first switch device (SW_1), including a first terminal coupled to an I/O voltage (V_DDIO), and including a second terminal, wherein the first switch device (SW_1) provides an initial driving voltage (V_di) at the second terminal of the first switch device (SW_1) ; and a first voltage providing device (D_vp1), including a first terminal coupled to the second terminal of the first switch device (SW_1), and comprising a second terminal. The first voltage providing device (D_vp1) is configured to provide a driving voltage at the second terminal of the first voltage providing device (D_VP1) via providing a voltage drop to the initial driving voltage (V_di).

公开(公告)号：EP3041142B1

公开(公告)日：2019-08-07

申请号：EP15185464.3

申请日：2015-09-16

申请人： MediaTek Inc.

发明人： CHEN, Shang-Pin ,  LI, An-Siou

IPC分类号： H03K19/0185

公开(公告)号：EP3041141B1

公开(公告)日：2017-07-12

申请号：EP15195296.7

申请日：2015-11-19

申请人： MediaTek Inc.

发明人： CHIANG, Chen-Feng ,  LI, An-Siou

IPC分类号： H03K19/00 ,  H03K19/003 ,  H03K19/0185

CPC分类号： H03K17/6871 ,  H03K17/08142 ,  H03K17/693 ,  H03K19/0027 ,  H03K19/00384 ,  H03K19/018521

摘要： An I/O driving circuit including a post driver (200, 300, 403, 503, 603), wherein the post driver (200, 300, 403, 503, 603) includes: a first switch device (SW_1), including a first terminal coupled to an I/O voltage (V_DDIO), and including a second terminal, wherein the first switch device (SW_1) provides an initial driving voltage (V_di) at the second terminal of the first switch device (SW_1) ; and a first voltage providing device (D_vp1), including a first terminal coupled to the second terminal of the first switch device (SW_1), and comprising a second terminal. The first voltage providing device (D_vp1) is configured to provide a driving voltage at the second terminal of the first voltage providing device (D_VP1) via providing a voltage drop to the initial driving voltage (V_di).

摘要翻译： 1。一种I / O驱动电路，其包括后驱动器（200,300,403,503,603），其中所述后驱动器（200,300,403,503,603）包括：第一开关装置（SW_1），其包括第一开关装置 （V_DDIO），并且包括第二端子，其中所述第一开关器件（SW_1）在所述第一开关器件（SW_1）的所述第二端子处提供初始驱动电压（V_di）;以及第二开关器件 以及第一电压提供装置（D_vp1），包括耦合到第一开关装置（SW_1）的第二端子的第一端子，并且包括第二端子。 第一电压提供装置（D_vp1）被配置为通过向初始驱动电压（V_di）提供电压降来在第一电压提供装置（D_VP1）的第二端子处提供驱动电压。

公开(公告)号：EP3041141A3

公开(公告)日：2016-10-26

申请号：EP15195296.7

申请日：2015-11-19

申请人： MediaTek, Inc

发明人： CHIANG, Chen-Feng ,  LI, An-Siou

IPC分类号： H03K19/00 ,  H03K19/003 ,  H03K19/0185

CPC分类号： H03K17/6871 ,  H03K17/08142 ,  H03K17/693 ,  H03K19/0027 ,  H03K19/00384 ,  H03K19/018521

摘要： An I/O driving circuit including a post driver (200, 300, 403, 503, 603), wherein the post driver (200, 300, 403, 503, 603) includes: a first switch device (SW_1), including a first terminal coupled to an I/O voltage (V_DDIO), and including a second terminal, wherein the first switch device (SW_1) provides an initial driving voltage (V_di) at the second terminal of the first switch device (SW_1) ; and a first voltage providing device (D_vp1), including a first terminal coupled to the second terminal of the first switch device (SW_1), and comprising a second terminal. The first voltage providing device (D_vp1) is configured to provide a driving voltage at the second terminal of the first voltage providing device (D_VP1) via providing a voltage drop to the initial driving voltage (V_di).

摘要翻译： 一种包括后置驱动器（200,300,403,503,603）的I / O驱动电路，其中所述后驱动器（200,300,403,503,603）包括：第一开关器件（SW_1），包括第一 并且包括第二端子，其中第一开关装置（SW_1）在第一开关装置（SW_1）的第二端提供初始驱动电压（V_di）; 以及第一电压提供装置（D_vp1），包括耦合到第一开关装置（SW_1）的第二端子的第一端子，并且包括第二端子。 第一电压提供装置（D_vp1）被配置为通过向初始驱动电压（V_di）提供电压降来在第一电压提供装置（D_VP1）的第二端提供驱动电压。

公开(公告)号：EP3041142A3

公开(公告)日：2016-09-28

申请号：EP15185464.3

申请日：2015-09-16

申请人： MediaTek, Inc

发明人： CHEN, Shang-Pin ,  LI, An-Siou

IPC分类号： H03K19/0185

CPC分类号： H03K19/017509 ,  G11C7/1057 ,  G11C7/1084 ,  H03K19/018507

摘要： A method for performing signal driving control in an electronic device (100, 300) and an associated apparatus (100, 300) are provided. The method includes: generating a first driving control signal (MOD1) and a second driving control signal (MOD2) according to a data signal (DATA), wherein the second driving control signal (MOD2) transits in response to a transition of the data signal (DATA), and the first driving control signal (MOD1) includes a pulse corresponding to the transition of the data signal (DATA); and utilizing a first switching unit to control a first signal path between a first voltage level (LEVEL1, SUP1) and an output terminal (OUT) of an output stage according to the first driving control signal (MOD1), and utilizing a second switching unit to control a second signal path between the first voltage level (LEVEL1, SUP1) and the output terminal (OUT) according to the second driving control signal (MOD2), wherein a first impedance (Z1) of the first signal path is less than a second impedance (Z2) of the second signal path.