公开(公告)号：EP3200569A1

公开(公告)日：2017-08-02

申请号：EP17153250.0

申请日：2017-01-26

申请人： MediaTek Inc.

发明人： CHANG, Chun-Wei ,  CHEN, Shang-Pin

IPC分类号： H05K1/02 ,  H01L23/48 ,  H01L23/552 ,  H04B3/32

CPC分类号： H05K1/0218 ,  H01L23/48 ,  H01L23/552 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/1436 ,  H01L2924/15192 ,  H04B3/32 ,  H05K1/0219 ,  H05K1/0228 ,  H05K1/0243 ,  H05K2201/10159 ,  H05K2201/10212

摘要： An integrated circuit is provided. The integrated circuit includes a control circuitry 160, a plurality of pins 150 coupled to a plurality of conductive traces 190 of a printed circuit board (PCB) 120, and a plurality of driving units DU coupled to the pins. The control circuitry provides a plurality of control signals Ctrl according to data to be transmitted. The driving units are divided into a plurality of first driving units and second driving units. According to the control signals, the first driving units provide the data to a memory device 130 mounted on the PCB via the corresponding pins 170 and the corresponding conductive traces of PCB, and the second driving units provide a constant voltage to the corresponding conductive traces 170 of PCB via the corresponding pin. The conductive traces corresponding to the second driving units form guard traces and separate the conductive traces corresponding to the first driving units which form signal traces on the PCB.

摘要翻译： 提供集成电路。 集成电路包括控制电路160，耦合到印刷电路板（PCB）120的多个导电迹线190的多个引脚150以及耦合到引脚的多个驱动单元DU。 控制电路根据待传输的数据提供多个控制信号Ctrl。 驱动单元被分成多个第一驱动单元和第二驱动单元。 根据控制信号，第一驱动单元通过相应的引脚170和PCB的相应导电迹线将数据提供给安装在PCB上的存储器件130，并且第二驱动单元向相应的导电迹线170提供恒定电压 的PCB通过相应的引脚。 对应于第二驱动单元的导电迹线形成防护迹线并且分离对应于在PCB上形成信号迹线的第一驱动单元的导电迹线。

公开(公告)号：EP3041142A3

公开(公告)日：2016-09-28

申请号：EP15185464.3

申请日：2015-09-16

申请人： MediaTek, Inc

发明人： CHEN, Shang-Pin ,  LI, An-Siou

IPC分类号： H03K19/0185

CPC分类号： H03K19/017509 ,  G11C7/1057 ,  G11C7/1084 ,  H03K19/018507

摘要： A method for performing signal driving control in an electronic device (100, 300) and an associated apparatus (100, 300) are provided. The method includes: generating a first driving control signal (MOD1) and a second driving control signal (MOD2) according to a data signal (DATA), wherein the second driving control signal (MOD2) transits in response to a transition of the data signal (DATA), and the first driving control signal (MOD1) includes a pulse corresponding to the transition of the data signal (DATA); and utilizing a first switching unit to control a first signal path between a first voltage level (LEVEL1, SUP1) and an output terminal (OUT) of an output stage according to the first driving control signal (MOD1), and utilizing a second switching unit to control a second signal path between the first voltage level (LEVEL1, SUP1) and the output terminal (OUT) according to the second driving control signal (MOD2), wherein a first impedance (Z1) of the first signal path is less than a second impedance (Z2) of the second signal path.

公开(公告)号：EP3418902A3

公开(公告)日：2019-03-13

申请号：EP18169189.0

申请日：2018-04-25

申请人： MediaTek Inc.

发明人： WU, Chung-Hwa ,  CHEN, Shang-Pin

IPC分类号： G06F13/40

摘要： The present invention provides a memory module wherein the memory module includes a plurality of memory devices having at least a first memory device and a second memory device, and the first memory device comprises a first termination resistor, and the second memory device comprises a second termination resistor. In the operations of the memory module, when the first memory device is accessed by a memory controller and the second memory device is not accessed by the memory controller, the first termination resistor is controlled to not provide impedance matching for the first memory device, and the second termination resistor is controlled to provide impedance matching for the second memory device.

公开(公告)号：EP3128516A1

公开(公告)日：2017-02-08

申请号：EP16178385.7

申请日：2016-07-07

申请人： MediaTek Inc.

发明人： LI, An-Siou ,  CHEN, Shang-Pin

IPC分类号： G11C7/10 ,  G11C5/14

CPC分类号： H03K17/687 ,  G11C5/14 ,  G11C7/1057 ,  G11C7/1069 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

摘要： An apparatus (100) for performing signal driving in an electronic device (100) may include a decoupling capacitor and at least one switching unit (SW1, SW2). The decoupling capacitor may have a first terminal and a second terminal, and may be positioned in an output stage within the electronic device (100) and coupled between a first predetermined voltage level and another predetermined voltage level, where the apparatus (100) may perform signal driving with aid of the output stage. In addition, the aforementioned at least one switching unit (SW1, SW2) may be coupled between one terminal of the first and the second terminals of the decoupling capacitor and at least one of the first predetermined voltage level and the other predetermined voltage level, and may be arranged for selectively disabling the decoupling capacitor.

摘要翻译： 用于执行信号驱动到电子设备（100）的装置（100）可以包括去耦电容器和至少一个切换单元（SW1，SW2）。 去耦电容器可以具有第一端子和第二端子，并且可在向电子设备（100）内的输出级被定位和连接第一预定电压电平与另一个预定电压电平，其中，所述设备（100）可以执行之间 信号与所述输出级的辅助驱动。 另外，上述的至少一个开关单元（SW1，SW2）可在第一的一个端子和去耦电容器的第二端子和第一预定电压电平中的至少一个和另一个预定的电压电平之间，以及被耦合 可以布置成用于选择性地禁止所述去耦电容器。

公开(公告)号：EP3208806A1

公开(公告)日：2017-08-23

申请号：EP17156430.5

申请日：2017-02-16

申请人： MediaTek Inc.

发明人： CHEN, Shang-Pin ,  HSIEH, Bo-Wei

IPC分类号： G11C11/4093 ,  G11C11/4076 ,  G11C7/22 ,  G11C7/10 ,  G11C5/04 ,  G06F13/40 ,  H03K19/00 ,  H04L25/02

CPC分类号： G11C11/4076 ,  G06F13/4086 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4093 ,  G11C2207/105 ,  H03K19/0005 ,  H04L25/0298

摘要： A memory system (100) includes a memory controller (110) and a memory module (120). The memory controller (110) is arranged for selectively generating at least a clock signal and an inverted clock signal. The memory module (120) includes a first termination resistor (ODT1), a second termination resistor (ODT2) and a switch module (222), where a first node of the first termination resistor (ODT1) is to receive the clock signal, a first node of the second termination resistor (ODT2) is to receive the inverted clock signal, and the switch module (222) is arranged for selectively connecting or disconnecting a second node of the second termination resistor (ODT2) to a second node of the first termination resistor (ODT1).

摘要翻译： 存储器系统（100）包括存储器控制器（110）和存储器模块（120）。 存储器控制器（110）被布置为选择性地产生至少时钟信号和反相时钟信号。 存储器模块120包括第一终端电阻ODT1，第二终端电阻ODT2和开关模块222，第一终端电阻ODT1的第一节点接收时钟信号， 第二端接电阻器（ODT2）的第一节点将接收反相时钟信号，并且开关模块（222）被布置为选择性地将第二端接电阻器（ODT2）的第二节点连接到或断开到第一节点 终端电阻（ODT1）。

公开(公告)号：EP3203476A1

公开(公告)日：2017-08-09

申请号：EP16186784.1

申请日：2016-09-01

申请人： MediaTek Inc.

发明人： CHEN, Shang-Pin ,  CHAN, Chia-Yu ,  HSIEH, Bo-Wei

IPC分类号： G11C7/22 ,  G11C11/4093 ,  G11C7/10 ,  G11C5/06

摘要： A memory interface circuit (122) includes a plurality of receivers (220_1-220_M) and a signal detector (210). The plurality of receivers (220_1-220_M) are arranged for receiving at least a clock signal and a plurality of command signals from a memory controller (110), respectively. The signal detector (210) is arranged for detecting whether the memory interface circuit (122) receives the clock signal or not to generate a detection result to enable or disable the plurality of receivers (220_1-220_M).

摘要翻译： 存储器接口电路（122）包括多个接收器（220_1-220_M）和信号检测器（210）。 多个接收器（220_1-220_M）被布置为分别从存储器控制器（110）接收至少一个时钟信号和多个命令信号。 信号检测器（210）用于检测存储器接口电路（122）是否接收到时钟信号以产生检测结果以启用或禁用多个接收器（220_1-220_M）。

公开(公告)号：EP3101438A1

公开(公告)日：2016-12-07

申请号：EP16167532.7

申请日：2016-04-28

申请人： MediaTek Inc.

发明人： CHEN, Shang-Pin ,  LEE, Sheng-Feng

IPC分类号： G01R31/317 ,  H02M1/00 ,  H03L1/00

CPC分类号： H03L1/00 ,  G01R31/31709 ,  H03L7/00 ,  H04L7/0087 ,  H04L7/065

摘要： A jitter control circuit (100) within a chip (102) includes an adaptive PDN (1 10), a current generator (120) and a jitter generator (160). The adaptive PDN (110) is capable of being controlled/modulated to provide difference impedances. The current generator (120) is coupled to the adaptive PDN (110), and is arranged for receiving a supply voltage provided by the adaptive PDN (110) and generating currents with different patterns. The jitter generator is coupled to the adaptive PDN (1 10), and is arranged for generating a plurality of jitters corresponding to the currents with different patterns, respectively, according to the supply voltage provided by the adaptive PDN (110).

摘要翻译： 芯片（102）内的抖动控制电路（100）包括自适应PDN（110），电流发生器（120）和抖动发生器（160）。 自适应PDN（110）能够被控制/调制以提供差分阻抗。 电流发生器（120）耦合到自适应PDN（110），并且被布置为接收由自适应PDN（110）提供的电源电压并且产生具有不同模式的电流。 抖动发生器耦合到自适应PDN（110），并且被配置为根据自适应PDN（110）提供的电源电压分别产生与具有不同模式的电流相对应的多个抖动。

公开(公告)号：EP3041142A2

公开(公告)日：2016-07-06

申请号：EP15185464.3

申请日：2015-09-16

申请人： MediaTek, Inc

发明人： CHEN, Shang-Pin ,  LI, An-Siou

IPC分类号： H03K19/0185

CPC分类号： H03K19/017509 ,  G11C7/1057 ,  G11C7/1084 ,  H03K19/018507

摘要： A method for performing signal driving control in an electronic device (100, 300) and an associated apparatus (100, 300) are provided. The method includes: generating a first driving control signal (MOD1) and a second driving control signal (MOD2) according to a data signal (DATA), wherein the second driving control signal (MOD2) transits in response to a transition of the data signal (DATA), and the first driving control signal (MOD1) includes a pulse corresponding to the transition of the data signal (DATA); and utilizing a first switching unit to control a first signal path between a first voltage level (LEVEL1, SUP1) and an output terminal (OUT) of an output stage according to the first driving control signal (MOD1), and utilizing a second switching unit to control a second signal path between the first voltage level (LEVEL1, SUP1) and the output terminal (OUT) according to the second driving control signal (MOD2), wherein a first impedance (Z1) of the first signal path is less than a second impedance (Z2) of the second signal path.

摘要翻译： 提供了一种用于在电子设备（100，300）和相关联的设备（100，300）进行信号的驱动控制方法。 该方法包括：响应于所述数据信号的转变产生雅丁第一驱动控制信号（MOD 1）和第二驱动控制信号（MOD 2）的数据信号（DATA），worin第二驱动控制信号（MOD 2）转变 （DATA），并且所述第一驱动控制信号（MOD 1）包括一脉冲对应于数据信号（DATA）的过渡; 与利用一个第一开关单元，用于控制第一电压电平（LEVEL1，SUP1）和输出级雅丁到第一驱动控制信号的输出端（OUT）（MOD 1）之间的第一信号路径，和利用第二开关单元 来控制所述第一电压电平（LEVEL1，SUP1）和雅丁到第二驱动控制信号（MOD 2）worin所述第一信号路径的第一阻抗（Z1）小于所述输出端（OUT）之间的第二信号路径 所述第二信号路径的第二阻抗（Z2）。

公开(公告)号：EP3203476B1

公开(公告)日：2019-10-30

申请号：EP16186784.1

申请日：2016-09-01

申请人： MediaTek Inc.

发明人： CHEN, Shang-Pin ,  CHAN, Chia-Yu ,  HSIEH, Bo-Wei

IPC分类号： G11C7/22 ,  G11C11/4093 ,  G11C7/10 ,  G11C5/06

公开(公告)号：EP3462485A1

公开(公告)日：2019-04-03

申请号：EP18193346.6

申请日：2018-09-10

申请人： MediaTek Inc.

发明人： HO, Duen-Yi ,  CHEN, Hung-Chuan ,  CHEN, Shang-Pin

IPC分类号： H01L23/538

摘要： A semiconductor device includes a substrate, a die and multiple conductive traces. The die is mounted on the substrate. The conductive traces are routed on the substrate and connected to the die. The conductive traces at least include a plurality of first conductive traces and a plurality of second conductive traces. The second conductive traces are coupled to a predetermined voltage for providing a shielding pattern. The first conductive traces and the second conductive traces are disposed on the substrate in a substantially interlaced pattern.