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393 条记录 (耗时 0.017 秒)

    VOLTAGE DRIVER CIRCUIT FOR FLASH MEMORY DEVICES
    2.
    发明授权
    VOLTAGE DRIVER CIRCUIT FOR FLASH MEMORY DEVICES 有权

    公开(公告)号：EP3107106B1

    公开(公告)日：2018-10-31

    申请号：EP15172890.4

    申请日：2015-06-19

    申请人： NXP B.V.

    发明人： Storms, Maurits ,  Ostertun, Soenke ,  Cevela, Frantisek

    IPC分类号： G11C16/30 ,  G11C16/08 ,  H03K3/356 ,  G11C5/14 ,  G11C8/08

    CPC分类号： H03K3/356182 ,  G11C5/14 ,  G11C5/147 ,  G11C8/08 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  H02M3/07 ,  H03K3/35613

    摘要： There is described a driver circuit (100) for providing biasing voltages to a flash memory device, the driver circuit comprising (a) a level shifter latch (110) comprising a first latch input terminal (111), a first latch control terminal (112), a latch voltage supply terminal (113), a first latch output terminal (114), and a second latch output terminal (115), wherein the level shifter latch (110) is adapted to provide, in dependency of a voltage at the first latch input terminal (111), one of a first voltage and a second voltage at the first latch output terminal (114) and the other one of the first voltage and the second voltage at the second latch output terminal (115), wherein the first voltage is dependent on a voltage applied to the latch voltage supply terminal (113) and the second voltage is dependent on a voltage applied to the first latch control terminal (112), (b) a first output stage (120) comprising a first switching element (N11, N12), a second switching element (N13), a first voltage supply terminal (122), a second voltage supply terminal (124), and a first biasing voltage output terminal (126), wherein the first switching element (N11, N12) is adapted to connect the first biasing voltage output terminal (126) to the first voltage supply terminal (122) in dependency of the voltage at the first latch output terminal (114), and wherein the second switching element (N13) is adapted to connect the first biasing voltage output terminal (126) to the second voltage supply terminal (124) in dependency of the voltage at the second latch output terminal (115), and (c) a second output stage (130) comprising a third switching element (N21), a fourth switching element (N22), a third voltage supply terminal (132), a fourth voltage supply terminal (134), and a second biasing voltage output terminal (136), wherein the third switching element (N21) is adapted to connect the second biasing voltage output terminal (136) to the third voltage supply terminal (132) in dependency of the voltage at the first latch output terminal (114), and wherein the fourth switching element (N22) is adapted to connect the second biasing voltage output terminal (136) to the fourth voltage supply terminal (134) in dependency of the voltage at the second latch output terminal (115).There is also described a memory system and a method of operating the driver circuit.

    MEMORY ACCESS CONTROL
    3.
    发明公开
    MEMORY ACCESS CONTROL 审中-公开

    公开(公告)号：EP3332331A1

    公开(公告)日：2018-06-13

    申请号：EP16833476.1

    申请日：2016-07-05

    申请人： Intel Corporation

    发明人： HAQUE, Rezaul ,  PINILLA PICO, Lady Nataly

    IPC分类号： G06F13/16 ,  G06F3/06

    CPC分类号： G06F3/0644 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0679 ,  G06F3/0688 ,  G11C5/14 ,  G11C7/1063 ,  G11C7/222

    摘要： The present disclosure relates to memory array access control. An apparatus includes partition control circuitry to control at least one partition of a memory array, the at least one partition control circuitry also to receive a controlled clock signal to enable execution of a legitimate memory access command and to generate an active/idle signal having an active state when executing the legitimate memory access command and an idle state when executing the legitimate memory access command is complete; wherein the clock signal is disabled when the active/idle signal is in an idle state.

    DATA TRANSFER ACROSS POWER DOMAINS
    4.
    发明授权
    DATA TRANSFER ACROSS POWER DOMAINS 有权

    公开(公告)号：EP2926279B1

    公开(公告)日：2018-06-13

    申请号：EP13811060.6

    申请日：2013-11-27

    申请人： Qualcomm Incorporated

    发明人： XIE, Jing ,  DU, Yang

    IPC分类号： G06F1/32

    CPC分类号： G06F17/5072 ,  G06F1/32 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/62 ,  G11C5/14 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/0008 ,  Y02D10/171 ,  H01L2924/00

    摘要： Exemplary embodiments of the invention are directed to systems and method for designing a clock distribution network for an integrated circuit. The embodiments identify critical sources of clock skew, tightly control the timing of the clock and build that timing into the overall clock distribution network and integrated circuit design. The disclosed embodiments separate the clock distribution network (CDN), i.e., clock generation circuitry, wiring, buffering and registers, from the rest of the logic to improve the clock tree design and reduce the area footprint. In one embodiment, the CDN is separated to a separate tier of a 3D integrated circuit, and the CDN is connected to the logic tier(s) via high-density inter-tier vias. The embodiments are particularly advantageous for implementation with monolithic 3D integrated circuits.

    RETENTION VOLTAGE GENERATION CIRCUIT AND ELECTRONIC APPARATUS
    6.
    发明公开
    RETENTION VOLTAGE GENERATION CIRCUIT AND ELECTRONIC APPARATUS 审中-公开
    保持电压发生电路和电子设备

    公开(公告)号：EP3321762A1

    公开(公告)日：2018-05-16

    申请号：EP17200717.1

    申请日：2017-11-09

    申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

    发明人： TO-MING, Szeto Simon ,  WU, Lei

    IPC分类号： G05F3/24 ,  G11C5/14

    CPC分类号： G11C11/4125 ,  G05F3/24 ,  G11C5/14 ,  G11C5/143 ,  G11C11/417 ,  H02J4/00

    摘要： Retention voltage generation circuits and electronic apparatus are provided. An exemplary retention voltage generation circuit includes a driving circuit, configured to generate driving currents; a first retention voltage generation circuit, configured to generate a first retention voltage, the first retention voltage being substantially equal to a threshold voltage of an NMOS transistor in a power-consumption circuit; a second retention voltage generation circuit, configured to generate a second retention voltage, the second retention voltage being substantially equal to a threshold voltage of a PMOS transistor in the power-consumption circuit; and a retention voltage selection circuit, coupled to the first retention voltage generation circuit and the second retention voltage generation circuit, and configured to receive the driving currents, wherein retention voltage selection circuit is configured to select a higher voltage from the first retention voltage and the second retention voltage as a retention voltage to drive the power-consumption circuit to operate at a retention mode.

    摘要翻译： 提供保持电压产生电路和电子设备。 示例性保持电压生成电路包括：驱动电路，被配置为生成驱动电流; 第一保持电压生成电路，被配置为生成第一保持电压，所述第一保持电压基本上等于功耗电路中的NMOS晶体管的阈值电压; 第二保持电压生成电路，被配置为生成第二保持电压，所述第二保持电压基本上等于所述功耗电路中的PMOS晶体管的阈值电压; 以及保持电压选择电路，与所述第一保持电压生成电路和所述第二保持电压生成电路耦合，并且被配置为接收所述驱动电流，其中保持电压选择电路被配置为从所述第一保持电压和所述第二保持电压中选择更高的电压， 第二保持电压作为保持电压以驱动功耗电路以保持模式工作。

    MEMORY CARD
    7.
    发明公开
    MEMORY CARD 审中-公开
    存储卡

    公开(公告)号：EP3161577A1

    公开(公告)日：2017-05-03

    申请号：EP15815061.5

    申请日：2015-06-30

    申请人： Samsung Electronics Co., Ltd.

    发明人： HAN, Seok-Jae ,  LIM, Gwang-Man ,  KANG, Il-Mok ,  KANG, Sang-Chul ,  KWON, Seok-Cheon ,  LEE, Seok-Chan

    IPC分类号： G06F1/00

    CPC分类号： G06F13/4068 ,  G06F13/1668 ,  G06K13/08 ,  G06K19/07732 ,  G06K19/07743 ,  G11C5/14

    摘要： Provided is a memory card, which includes two pairs of opposite edges, first row terminals arranged adjacent to an insertion-side edge of the memory card, and second row terminals arranged apart from the insertion-side edge of the memory card. The memory card can be easily reset in terms of software without controlling power supply in terms of hardware. Also, the memory card can be smoothly attached and detached during insertion of the memory card into a socket and reduce damage to a device.

    摘要翻译： 提供一种存储卡，其包括两对相对的边缘，与存储卡的插入侧边缘相邻布置的第一行端子，以及与存储卡的插入侧边缘分开布置的第二行端子。 硬件方面，无需控制电源即可轻松对软件进行复位。 另外，在将存储卡插入插座时，存储卡可以平滑地连接和拆卸，并减少对设备的损坏。

    WRITE DRIVER FOR WRITE ASSISTANCE IN MEMORY DEVICE
    10.
    发明公开
    WRITE DRIVER FOR WRITE ASSISTANCE IN MEMORY DEVICE 有权
    写驱动器，用于在存储设备写入支持

    公开(公告)号：EP2954528A1

    公开(公告)日：2015-12-16

    申请号：EP14703757.6

    申请日：2014-01-30

    申请人： Qualcomm Incorporated

    发明人： JUNG, Changho ,  DESAI, Nishith ,  VATTIKONDA, Rakesh

    IPC分类号： G11C11/419

    CPC分类号： G11C7/12 ,  G11C5/14 ,  G11C7/00 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/419

    摘要： A write assist driver circuit is provided that assists a memory cell (e.g., volatile memory bit cell) in write operations to keep the voltage at the memory core sufficiently high for correct write operations, even when the supply voltage is lowered. The write assist driver circuit may be configured to provide a memory supply voltage VddM to a bit cell core during a standby mode of operation. In a write mode of operation, the write assist driver circuit may provide a lowered memory supply voltage VddM
    lower to the bit cell core as well as to at least one of the local write bitline (lwbl) and local write bitline bar (lwblb). Additionally, the write assist driver circuit may also provide a periphery supply voltage VddP to a local write wordline (lwwl), where VddP ≥ VddM > VddM
    lower .