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    MULTI-STATE MEMORY CELL WITH ASYMMETRIC CHARGE TRAPPING
    2.
    发明公开
    MULTI-STATE MEMORY CELL WITH ASYMMETRIC CHARGE TRAPPING 审中-公开
    具有不对称LOAD事件的详细状态存储器单元

    公开(公告)号：EP1719185A1

    公开(公告)日：2006-11-08

    申请号：EP05713587.3

    申请日：2005-02-15

    申请人： MICRON TECHNOLOGY, INC.

    发明人： PRALL, Kirk

    IPC分类号： H01L29/792 ,  H01L29/788

    CPC分类号： H01L29/7887 ,  H01L29/7923

    摘要： A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide - nitride - oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide - nitride - oxide structure. An asymmetrical bias on the drain/source areas causes the drain/source area with the higher voltage to inject an asymmetric distribution hole by gate induced drain leakage injection into the trapping layer substantially adjacent that drain/source area.

    MEMORY CELL IMPRINT AVOIDANCE
    4.
    发明公开
    MEMORY CELL IMPRINT AVOIDANCE 审中-公开

    公开(公告)号：EP3926629A1

    公开(公告)日：2021-12-22

    申请号：EP21189181.7

    申请日：2017-06-02

    申请人： Micron Technology, Inc.

    发明人： CALDERONI, Alessandro ,  RAMASWAMY, Durai Vishak Nirmal ,  PRALL, Kirk ,  BEDESCHI, Ferdinando

    IPC分类号： G11C11/22 ,  G11C7/10 ,  G11C29/52 ,  G06F11/10 ,  G11C7/04

    摘要： Method and electronic memory device to avoid imprint in a ferroelectric memory, the electronic memory device, comprising:
    a memory cell;
    a latch coupled with the memory cell; and
    a sense component coupled with the memory cell and the latch, the sense component operable to:
    determine a first logic state stored on the memory cell;
    receive an indicator stored on the latch indicating whether the first logic state stored on the memory cell is an intended logic state; and
    output a second logic state different from the first logic state stored on the memory cell based at least in part on the indicator stored on the latch.

    NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AN METHODS
    6.
    发明公开
    NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AN METHODS 审中-公开
    NROM存储单元，存储器阵列中，相关的设备和方法

    公开(公告)号：EP1530803A2

    公开(公告)日：2005-05-18

    申请号：EP03761130.8

    申请日：2003-06-19

    申请人： MICRON TECHNOLOGY, INC.

    发明人： PRALL, Kirk ,  FORBES, Leonard

    IPC分类号： H01L27/115

    CPC分类号： H01L29/7926 ,  G11C11/5692 ,  G11C16/0466 ,  G11C16/0475 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7923

    摘要： An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures (34) providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

    A 2F?2 MEMORY DEVICE SYSTEM AND METHOD
    7.
    发明公开
    A 2F?2 MEMORY DEVICE SYSTEM AND METHOD 审中-公开
    半导体存储组件和方法

    公开(公告)号：EP1366525A2

    公开(公告)日：2003-12-03

    申请号：EP02750562.7

    申请日：2002-02-27

    申请人： MICRON TECHNOLOGY, INC.

    发明人： PRALL, Kirk

    IPC分类号： H01L27/115 ,  H01L21/8247

    CPC分类号： H01L27/11556 ,  H01L27/115 ,  H01L29/7883

    摘要： Methods and devices are disclosed which provide for memory devices having reduced memory cell square feature sizes. Such square feature sizes can permit large memory devices, on the order of a gigabyte or large, to be fabricated on one chip or die. The methods and devices disclosed, along with variations of them, utilize three dimensions as opposed to other memory devices which are fabricated in only two dimensions. Thus, the methods and devices disclosed , along with variations, contains substantially horizontal and vertical components.