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    RESISTANCE VARIABLE MEMORY SENSING
    3.
    发明公开
    RESISTANCE VARIABLE MEMORY SENSING 审中-公开
    艾滋病毒感染者麻醉病毒VERNDDERLICHEM WIDERSTAND

    公开(公告)号：EP2989634A1

    公开(公告)日：2016-03-02

    申请号：EP14787966.2

    申请日：2014-04-15

    申请人： Micron Technology, Inc.

    发明人： BEDESCHI, Ferdinando ,  GASTALDI, Roberto

    IPC分类号： G11C13/00 ,  G11C7/06

    CPC分类号： G11C13/004 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057 ,  G11C2013/0076

    摘要： The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include programming a memory cell to an initial data state and determining a data state of the memory cell by applying a programming signal to the memory cell, the programming signal associated with programming memory cells to a particular data state, and determining whether the data state of the memory cell changes from the initial data state to the particular data state during application of the programming signal.

    摘要翻译： 本公开包括用于感测电阻变量存储单元的装置和方法。 许多实施例包括将存储器单元编程为初始数据状态，并通过向存储器单元施加编程信号来确定存储器单元的数据状态，将编程信号与编程存储器单元相关联到特定数据状态，以及确定是否 在应用编程信号期间，存储单元的数据状态从初始数据状态变为特定数据状态。

    MEMORY CELL IMPRINT AVOIDANCE
    5.
    发明公开
    MEMORY CELL IMPRINT AVOIDANCE 审中-公开

    公开(公告)号：EP3926629A1

    公开(公告)日：2021-12-22

    申请号：EP21189181.7

    申请日：2017-06-02

    申请人： Micron Technology, Inc.

    发明人： CALDERONI, Alessandro ,  RAMASWAMY, Durai Vishak Nirmal ,  PRALL, Kirk ,  BEDESCHI, Ferdinando

    IPC分类号： G11C11/22 ,  G11C7/10 ,  G11C29/52 ,  G06F11/10 ,  G11C7/04

    摘要： Method and electronic memory device to avoid imprint in a ferroelectric memory, the electronic memory device, comprising:
    a memory cell;
    a latch coupled with the memory cell; and
    a sense component coupled with the memory cell and the latch, the sense component operable to:
    determine a first logic state stored on the memory cell;
    receive an indicator stored on the latch indicating whether the first logic state stored on the memory cell is an intended logic state; and
    output a second logic state different from the first logic state stored on the memory cell based at least in part on the indicator stored on the latch.