公开(公告)号：EP3900042A2

公开(公告)日：2021-10-27

申请号：EP19901376.4

申请日：2019-12-05

申请人： Micron Technology, Inc.

发明人： CASTRO, Hernan A. ,  RUSSELL, Stephen W. ,  TANG, Stephen H.

IPC分类号： H01L27/12 ,  H01L29/786

公开(公告)号：EP3087564A1

公开(公告)日：2016-11-02

申请号：EP14874228.1

申请日：2014-12-02

申请人： Micron Technology, Inc.

发明人： TANG, Stephen H.

IPC分类号： G11C8/10 ,  G11C8/14

CPC分类号： G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069

摘要： Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.

公开(公告)号：EP4408152A2

公开(公告)日：2024-07-31

申请号：EP24182402.8

申请日：2019-03-28

申请人： MICRON TECHNOLOGY, INC.

发明人： CASTRO, Hernan A ,  TANG, Stephen H. ,  RUSSELL, Stephen W.

IPC分类号： H10N70/20

CPC分类号： G11C2213/7720130101 ,  G11C2213/7120130101 ,  G11C13/0004 ,  H10B63/82 ,  H10B63/84 ,  H10B63/80 ,  H10N70/245 ,  H10N70/882 ,  H10N70/8825 ,  H10N70/231 ,  H10N70/826 ,  H10N70/20 ,  H10N70/063 ,  H10N70/011

摘要： Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.