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公开(公告)号：EP4401127A2
公开(公告)日：2024-07-17
申请号：EP24176697.1
申请日：2019-04-30
发明人： LIU, Jun
IPC分类号： H01L23/31
CPC分类号： G11C11/005 , G11C16/0483 , G11C11/401 , H01L25/18 , H01L25/50 , H01L23/3114 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L2224/0559920130101 , H01L2224/0562420130101 , H01L2224/0564720130101 , H01L2224/0565720130101 , H01L2224/0568420130101 , H01L2224/0814520130101 , H01L2224/8035720130101 , H01L2224/9420130101 , H01L2225/0656520130101 , H01L2224/8089520130101 , H01L2224/8089620130101 , H01L27/0688 , H01L2225/0654120130101 , G11C11/5621 , G11C11/5678 , G11C2213/7120130101 , H01L24/05 , H01L24/29 , H01L24/83 , H01L2224/0564420130101 , H01L2224/2918620130101 , H01L2224/8389620130101 , H01L2224/8037920130101 , H10B63/30 , H10B63/84 , H10N70/231 , H10B12/50 , H10B43/40 , H10B43/27
摘要： Embodiments of three-dimensional (3D) memory devices with embedded dynamic random-access memory (DRAM) and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including a peripheral circuit, an array of embedded DRAM cells, and a first bonding layer including a plurality of first bonding contacts. The 3D memory device also further includes a second semiconductor structure including an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts. The 3D memory device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.
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公开(公告)号：EP4399708A1
公开(公告)日：2024-07-17
申请号：EP22881914.0
申请日：2022-10-05
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C13/0026 , G11C2213/7120130101 , G11C2213/7620130101 , G11C13/0028 , G11C5/025 , H10B63/84 , H10B63/10 , H10N70/20 , H10N70/826 , H10N70/8825 , H10N70/231 , H10B63/24
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公开(公告)号：EP4395525A2
公开(公告)日：2024-07-03
申请号：EP23185777.2
申请日：2023-07-17
发明人： KIM, Seyun , KANG, Jooheon , Yumin, KIM , PARK, Garam , SONG, Hyunjae , AHN, Dongho , YANG, Seungyeul , WOO, Myunghun , LEE, Jinwoo , HYUN, Seungdam
CPC分类号： H10N70/8833 , H10N70/24 , H10N70/8265 , H10N70/061 , H10N70/023 , H10B63/34 , H10B63/84 , H10N70/828
摘要： Disclosed is a resistive memory device (CS) including a vertical stack of memory cells (MC), each memory cell comprising a gate electrode (140), a resistance change layer (124), a (semiconductor transistor) channel (132) between the gate electrode and the resistance change layer, an island structure (128) between and in contact with the resistance change layer and the channel, and a gate insulating layer (136) between the gate electrode and the channel. Preferably, the island structure includes SiN, GaN, or an oxide having a greater absolute value of oxide formation energy than the resistance change layer. A method of fabricating such memory cells is also disclosed.
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4.发明公开
公开(公告)号：EP4354525A1
公开(公告)日：2024-04-17
申请号：EP22823900.0
申请日：2022-04-21
CPC分类号： H10N70/826 , H10N70/828 , H10N70/231 , H10N70/063 , H10N70/061 , H10B63/10 , H10B63/80 , H10B63/84
摘要： This application provides a phase change memory, an electronic device, and a preparation method for a phase change memory, and relates to the field of data storage technologies, to resolve problems such as low reliability and a short cycle life of the phase change memory. The phase change memory provided in this application includes a plurality of phase change memory cells. Each of the plurality of phase change memory cells includes a first electrode, a phase change body, and a second electrode, which are sequentially arranged in a first direction. The phase change body has a first end face facing the first electrode and a second end face facing the second electrode. The phase change body further includes a convergence portion, and the convergence portion is located between the first end face and the second end face, where a sectional area of the convergence portion in a direction perpendicular to the first direction is less than an area of the first end face and an area of the second end face. By arranging the convergence portion in the phase change body, a thermal effect is aggregated in the convergence portion, thereby having high reliability and a long cycle life.
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公开(公告)号：EP4408152A2
公开(公告)日：2024-07-31
申请号：EP24182402.8
申请日：2019-03-28
IPC分类号： H10N70/20
CPC分类号： G11C2213/7720130101 , G11C2213/7120130101 , G11C13/0004 , H10B63/82 , H10B63/84 , H10B63/80 , H10N70/245 , H10N70/882 , H10N70/8825 , H10N70/231 , H10N70/826 , H10N70/20 , H10N70/063 , H10N70/011
摘要： Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.
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公开(公告)号：EP3891799B1
公开(公告)日：2024-06-19
申请号：EP19927324.4
申请日：2019-04-30
CPC分类号： G11C11/005 , G11C16/0483 , G11C11/401 , H01L25/18 , H01L25/50 , H01L23/3114 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L2224/0559920130101 , H01L2224/0562420130101 , H01L2224/0564720130101 , H01L2224/0565720130101 , H01L2224/0568420130101 , H01L2224/0814520130101 , H01L2224/8035720130101 , H01L2224/9420130101 , H01L2225/0656520130101 , H01L2224/8089520130101 , H01L2224/8089620130101 , H01L27/0688 , H01L2225/0654120130101 , G11C11/5621 , G11C11/5678 , G11C2213/7120130101 , H01L24/05 , H01L24/29 , H01L24/83 , H01L2224/0564420130101 , H01L2224/2918620130101 , H01L2224/8389620130101 , H01L2224/8037920130101 , H10B63/30 , H10B63/84 , H10N70/231 , H10B12/50 , H10B43/40 , H10B43/27
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公开(公告)号：EP4395525A3
公开(公告)日：2024-09-18
申请号：EP23185777.2
申请日：2023-07-17
发明人： KIM, Seyun , KANG, Jooheon , Yumin, KIM , PARK, Garam , SONG, Hyunjae , AHN, Dongho , YANG, Seungyeul , WOO, Myunghun , LEE, Jinwoo , HYUN, Seungdam
CPC分类号： H10N70/8833 , H10N70/24 , H10N70/8265 , H10N70/061 , H10N70/023 , H10B63/34 , H10B63/84 , H10N70/828 , H10B43/35 , H10B43/10 , G11C16/0483 , H10B43/27
摘要： Disclosed is a resistive memory device (CS) including a vertical stack of memory cells (MC), each memory cell comprising a gate electrode (140), a resistance change layer (124), a (semiconductor transistor) channel (132) between the gate electrode and the resistance change layer, an island structure (128) between and in contact with the resistance change layer and the channel, and a gate insulating layer (136) between the gate electrode and the channel. Preferably, the island structure includes SiN, GaN, or an oxide having a greater absolute value of oxide formation energy than the resistance change layer. A method of fabricating such memory cells is also disclosed.
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公开(公告)号：EP3785308B1
公开(公告)日：2024-06-19
申请号：EP19791688.5
申请日：2019-03-28
CPC分类号： G11C2213/7720130101 , G11C2213/7120130101 , G11C13/0004 , H10B63/82 , H10B63/84 , H10B63/80 , H10N70/245 , H10N70/882 , H10N70/8825 , H10N70/231 , H10N70/061 , H10N70/826 , H10N70/20
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