AN ELECTRICAL DEVICE COMPRISING STACKED CAPACITIVE STRUCTURES WITH ELECTRODES CONNECTED FROM BOTTOM TO TOP AND TOP TO BOTTOM

    公开(公告)号:EP4184537A1

    公开(公告)日:2023-05-24

    申请号:EP21306605.3

    申请日:2021-11-18

    摘要: An electrical device comprising:
    a first stacked capacitive structure comprises N electrodes (E1_1, ..., E1_N), from the first to the N-th electrode, each having a 3D shape, and conformally stacked, the electrodes being all separated by N-1 dielectric layers so that N-1 stacked capacitors are formed in the first stacked capacitive structure,
    a second stacked capacitive structure comprises N electrodes (E2_1, ..., E2_N), from the first to the N-th electrode, each having a 3D shape, and conformally stacked, the electrodes being all separated by N-1 dielectric layers so that N-1 stacked capacitors are formed in the second stacked capacitive structure,
    further comprising N electrical connections (CN1_N, ..., CNN_1), wherein the X-th electrode of the first stacked capacitive structure is connected by an electrical connection to the N-X+1-th electrode of the second stacked capacitive structure.

    CONTACT STRUCTURES IN RC-NETWORK COMPONENTS
    2.
    发明公开

    公开(公告)号:EP3886163A1

    公开(公告)日:2021-09-29

    申请号:EP20305348.3

    申请日:2020-03-26

    摘要: RC-network components (101) are described which comprise a substrate (102) provided with a capacitor having a thin-film top electrode portion (107) at a surface on one side (102a) of the substrate. The resistance provided in series with the capacitor is controlled by providing a contact plate (109), spaced from the thin-film top electrode portion (107) by an insulating layer (110), and a set of bridging contacts (108) passing through openings (111) in the insulating layer (110). The bridging contacts electrically interconnect the thin-film top electrode portion (107) and the contact plate (109). Different resistance values can be set by appropriate selection of the number of bridging contacts (8) that are provided. Temperature concentration at the periphery of the openings (111) is reduced by making the openings (111) elongated. Correspondingly, the bridging contacts (8) have an elongated cross-sectional shape.

    AN ELECTRICAL DEVICE COMPRISING A COPLANAR WAVEGUIDE WITH BURIED BRIDGES AND APERTURES

    公开(公告)号:EP4037094A1

    公开(公告)日:2022-08-03

    申请号:EP21305103.0

    申请日:2021-01-27

    IPC分类号: H01P3/00

    摘要: An electrical device comprising a coplanar waveguide above a substrate (200) including a signal line (101) surrounded on one side by a first portion (103A) of ground plane and on another side by a second portion (103B) of ground plane,
    wherein the device further comprises at least one buried conductive bridge (120) forming an electrical connection between the first portion of the ground plane and to the second portion of the ground plane, the buried bridge being perpendicular with the signal line, arranged below the signal line, and being electrically insulated from the signal line by an insulating layer (140),
    and wherein the signal line comprises an aperture (110) above and at the level of the buried bridge arranged so that two portions (111A, 111B) of signal line remain on each side of the aperture.

    AN ELECTRICAL DEVICE COMPRISING A 3D CAPACITOR AND A REGION SURROUNDED BY A THROUGH OPENING

    公开(公告)号:EP4016566A1

    公开(公告)日:2022-06-22

    申请号:EP20306573.5

    申请日:2020-12-15

    摘要: An electrical device comprising:
    a substrate (100),
    a 3D capacitor (110) including a capacitor dielectric region (112) of a dielectric material, a capacitor electrode region (113) of a conductive material, the capacitor dielectric region and the capacitor electrode region being arranged at least partially inside a cavity (103) extending in the substrate from the top face of the substrate, and
    a surrounding through opening (104') formed in the substrate and which surrounds a surrounded substrate region (105), the 3D capacitor being outside of the surrounded substrate region, the surrounding through opening extending from the top face to the bottom face of the substrate,
    wherein inside the surrounding through opening a surrounding dielectric region (122) of the dielectric material and a surrounding conductive region (123) of the conductive material are arranged.
    The invention also relates to a method of manufacturing this device.

    IMPROVED 3D CAPACITORS
    8.
    发明公开

    公开(公告)号:EP3800676A1

    公开(公告)日:2021-04-07

    申请号:EP19306249.4

    申请日:2019-10-01

    IPC分类号: H01L49/02 H01L29/66 H01L29/94

    摘要: Three-dimensional capacitor components (101) are described which comprise a substrate (103) having a textured (contoured) surface and a stack of layers formed conformally over the textured surface to constitute a capacitive stack structure (5). Respective contacts (11,12) to the bottom and top electrodes of the capacitive stack structure are both provided at a first side (103a) of the component. The bottom electrode (6) and substrate (103) are doped with dopants of the same polarity, and the substrate is heavily doped so that current between a terminal portion (6r) of the bottom electrode and remote parts of the bottom electrode flows via the substrate, lowering ESR. A backside metallization layer (105) produces a further, and greater, reduction in ESR. The capacitor component (101) may be implemented as a discrete capacitor component, but may also be integrated with other components/devices. Corresponding fabrication methods are described.

    METHOD FOR FORMING AN ELECTRONIC PRODUCT COMPRISING TWO CAPACITORS HAVING DIFFERENT DIELECTRIC THICKNESSES, AND CORRESPONDING ELECTRONIC PRODUCT

    公开(公告)号:EP3621119A1

    公开(公告)日:2020-03-11

    申请号:EP18306164.7

    申请日:2018-09-04

    IPC分类号: H01L29/66 H01L27/08 H01L29/94

    摘要: A method for forming an electronic product comprising a first capacitor and a second capacitor, the electronic product comprising:
    - in a semi-conductor substrate (100), a bottom electrode region (101) of the first capacitor and a bottom electrode region of the second capacitor,
    - a first dielectric layer (106) having a first thickness arranged above the bottom electrode region of the first capacitor,
    - a second dielectric layer (108) having a second thickness arranged above the bottom electrode region of the second capacitor, the first thickness and the second thickness being different,
    - a top electrode region (111, 124) of the first capacitor arranged above the bottom electrode of the first capacitor and above the first dielectric layer,
    - a top electrode region (113, 125) of the second capacitor arranged above the bottom electrode of the second capacitor and above the second dielectric layer.