INTEGRATED DEVICE, SEMICONDUCTOR DEVICE, AND INTEGRATED DEVICE MANUFACTURING METHOD

    公开(公告)号:EP4325581A1

    公开(公告)日:2024-02-21

    申请号:EP21944601.0

    申请日:2021-06-11

    IPC分类号: H01L29/20 H01L27/01 H01G4/33

    摘要: An integrated device, a semiconductor device, and an integrated device manufacturing method are provided, to improve capacitor integration density of the integrated device. The integrated device in embodiments of this application includes: A first dielectric layer is disposed on a first metal layer; the first metal layer, the first dielectric layer, and a gate metal layer on the first dielectric layer form a first capacitor; the gate metal layer, a second dielectric layer on the gate metal layer, and a second metal layer on the second dielectric layer form a second capacitor; and the first metal layer is connected to the second metal layer through a first conductor structure, so that the first capacitor and the second capacitor are connected in parallel.

    CONDENSATEUR VERTICAL
    6.
    发明公开

    公开(公告)号:EP4220674A1

    公开(公告)日:2023-08-02

    申请号:EP23167146.2

    申请日:2019-09-18

    摘要: La présente description concerne un condensateur vertical (100a, 100b) comprenant un empilement de couches (108, 120) recouvrant de manière conforme au moins des murs (106) en un premier matériau, les murs s'étendant à partir d'un substrat en un deuxième matériau différent du premier.

    MICROELECTRONIC ASSEMBLIES HAVING INTEGRATED THIN FILM CAPACITORS

    公开(公告)号:EP4102556A1

    公开(公告)日:2022-12-14

    申请号:EP22177322.9

    申请日:2022-06-03

    申请人: INTEL Corporation

    摘要: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die in a first dielectric layer; and a capacitor including a first conductive pillar and a second conductive pillar in the first dielectric layer, each pillar having a first end and an opposing second end, where the first and second conductive pillars form a first plate of the capacitor; a second dielectric layer on the die and on the second end of the first and second conductive pillars extending at least partially along a first thickness of the first and second conductive pillars and tapering from the second end towards the first end; and a metal layer on the second dielectric layer, wherein the metal layer extends at least partially along a second thickness of the first and second conductive pillars, where the metal layer forms a second plate of the capacitor.