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公开(公告)号：EP0192410B1
公开(公告)日：1991-11-21
申请号：EP86300963.5
申请日：1986-02-12
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公开(公告)号：EP0192411A3
公开(公告)日：1988-08-03
申请号：EP86300964
申请日：1986-02-12
CPC分类号： H04L25/03057
摘要： High-speed bipolar signals transmitted along standard twisted pair (17) telephone wiring are subject to InterSymbol Interference which is corrected by an equalizer circuit (10) that is operably responsive to predetermined parameters of bipolar signals detected at the secondary (21) of a line transformer (15). These parameters are input to a control logic circuit (11) which includes several stages, each producing a set of past dependent logical control signals which are input to corresponding equalizer tap circuits (25) (26) (27) having outputs connected to a common output bus (40). Each tap circuit (25) (26) (27) includes an integrator (46) that is incrementally charged and discharged by an electronically switched capacitor (51). A tap weight voltage output from each integrator (46) is subsequently summed directly or inversely by a second switched capacitor (52) under control of the logical input signals. And, an equalizing signal output from the second capacitor (52) is coupled through a buffer amplifier (41) to the line transformer (15) where it is added to the incoming signal and allows eye diagram monitoring directly at the transformer (15).
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公开(公告)号：EP0192411A2
公开(公告)日：1986-08-27
申请号：EP86300964.3
申请日：1986-02-12
IPC分类号： H04L25/03
CPC分类号： H04L25/03057
摘要： High-speed bipolar signals transmitted along standard twisted pair (17) telephone wiring are subject to InterSymbol Interference which is corrected by an equalizer circuit (10) that is operably responsive to predetermined parameters of bipolar signals detected at the secondary (21) of a line transformer (15). These parameters are input to a control logic circuit (11) which includes several stages, each producing a set of past dependent logical control signals which are input to corresponding equalizer tap circuits (25) (26) (27) having outputs connected to a common output bus (40). Each tap circuit (25) (26) (27) includes an integrator (46) that is incrementally charged and discharged by an electronically switched capacitor (51). A tap weight voltage output from each integrator (46) is subsequently summed directly or inversely by a second switched capacitor (52) under control of the logical input signals. And, an equalizing signal output from the second capacitor (52) is coupled through a buffer amplifier (41) to the line transformer (15) where it is added to the incoming signal and allows eye diagram monitoring directly at the transformer (15).
摘要翻译： 沿着标准双绞线（17）电话线传输的高速双极性信号受到符号间干扰，该符号间干扰通过均衡器电路（10）进行校正，所述均衡器电路（10）可操作地响应在线路的次级（21）处检测到的双极性信号的预定参数 变压器（15）。 这些参数被输入到包括几个级的控制逻辑电路（11），每个级产生一组过去的相关逻辑控制信号，它们被输入到相应的均衡器抽头电路（25）（26）（27），其输出端连接到一个公共 输出总线（40）。 每个抽头电路（25）（26）（27）包括由电子开关电容器（51）递增充电和放电的积分器（46）。 随后在逻辑输入信号的控制下由每个积分器（46）输出的抽头加权电压直接或相反地被第二开关电容器（52）相加。 并且，从第二电容器（52）输出的均衡信号通过缓冲放大器（41）耦合到线路变压器（15），在那里它被加到输入信号并允许直接在变压器（15）上进行眼图监控。
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公开(公告)号：EP0192410A2
公开(公告)日：1986-08-27
申请号：EP86300963.5
申请日：1986-02-12
摘要： A stream of high-speed bipolar signals (18) (19) transmitted along standard twisted pair (13) telephone wiring are detected by a circuit (10) that includes a pair of differential amplifiers (20) (21) each having a signal input (11) (12) connected directly to one conductor (14) (15) of the twisted pair (13) and a reference input (22) (23) connected through a peak voltage detector (29) to the opposite conductor (14) (15). The amplifiers (20) (21) function as an input signal comparator which generates a corresponding bit stream of logical ones in response to the bipolar signals that exceed 50% of the average peak voltage input. A threshold bias voltage corresponding to positive going signals on each conductor (14) (15) is generated by the detector (29) and charges separate capacitors (37) (39) that connect each reference input (22) (23) to its conductor (14) (15). The bias voltage and bipolar signals input to each amplifier (20) (21) are algebraically summed which doubles the differential input signal and results in an increased signal to noise ratio of about six decibels.
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公开(公告)号：EP0192410A3
公开(公告)日：1988-10-26
申请号：EP86300963
申请日：1986-02-12
摘要： A stream of high-speed bipolar signals (18) (19) transmitted along standard twisted pair (13) telephone wiring are detected by a circuit (10) that includes a pair of differential amplifiers (20) (21) each having a signal input (11) (12) connected directly to one conductor (14) (15) of the twisted pair (13) and a reference input (22) (23) connected through a peak voltage detector (29) to the opposite conductor (14) (15). The amplifiers (20) (21) function as an input signal comparator which generates a corresponding bit stream of logical ones in response to the bipolar signals that exceed 50% of the average peak voltage input. A threshold bias voltage corresponding to positive going signals on each conductor (14) (15) is generated by the detector (29) and charges separate capacitors (37) (39) that connect each reference input (22) (23) to its conductor (14) (15). The bias voltage and bipolar signals input to each amplifier (20) (21) are algebraically summed which doubles the differential input signal and results in an increased signal to noise ratio of about six decibels.
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公开(公告)号：EP0138346A2
公开(公告)日：1985-04-24
申请号：EP84305889.2
申请日：1984-08-29
CPC分类号： H04L7/033 , H03K3/0307 , H03L7/099
摘要： A variable oscillator, suitable for integration as part of a phase lock loop (PLL) clock source in a complementary metal oxide semiconductor (CMOS) integrated circuit, includes an amplifier and terminals for connection to a a tank circuit, for example a crystal resonator. A passive reactance is alternately coupled and decoupled in relation to the amplifier to cause oscillatory operation at lower and higher frequencies. In the CMOS circuit the reactance is conveniently provided by conductive layers of predetermined dimensions being carried by an oxide layer. Each layer provides a capacitive reactance which is arranged in series with a field effect defice being controlled by associated PLL control circuitry.
摘要翻译： 适用于作为互补金属氧化物半导体（CMOS）集成电路中的锁相环（PLL）时钟源的一部分集成的可变振荡器包括用于连接到诸如晶体谐振器的电路的放大器和端子。 被动电抗相对于放大器交替耦合和解耦，以产生在较低和较高频率下的振荡操作。 在CMOS电路中，由氧化物层承载的预定尺寸的导电层方便地提供电抗。 每层提供容性电抗，该电抗与由相关的PLL控制电路控制的场效应相串联。
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公开(公告)号：EP0866559A1
公开(公告)日：1998-09-23
申请号：EP98300516.6
申请日：1998-01-26
IPC分类号： H03L7/089
CPC分类号： H03L7/113 , H03L7/0898
摘要： A phase-locked loop (PLL) includes a voltage controlled oscillator (VCO), a charge pump, a phase detector and a frequency detector. The phase detector detects the phase difference between an incoming signal and a VCO signal. The frequency difference between the incoming signal and a reference signal is detected by the frequency detector separately from the phase detector. During the process of attaining phase lock, the phase and frequency detectors operate simultaneously. The VCO signal is phase-locked to the incoming signal when it is present. When the incoming signal is absent, the VCO maintains a frequency close to an intended bit rate by frequency locking to a multiple of the reference signal. It, thus, avoids extreme system behavior and greatly assists rapid reliable phase lock when the incoming signal is applied following a period when it is absent. The PLL is analog for simplicity, low power, and the ability to achieve the finest possible phase resolution, while the frequency lock mode is digitally controlled for high parametric insensitivity and ease of disabling to minimize power consumption and jitter once phase lock is attained. The frequency detector includes two counters for counting the VCO and reference signals. The frequency detector inhibits either of the counters as needed to force them both to count at the same rate and uses inhibit pulses to control a separate charge pump connected directly to the integration capacitor of the PLL. The frequency detector can be easily added to a wide range of charge pump PLLs.
摘要翻译： 锁相环（PLL）包括压控振荡器（VCO），电荷泵，相位检测器和频率检测器。 相位检测器检测输入信号和VCO信号之间的相位差。 输入信号和参考信号之间的频率差由频率检测器与相位检测器分开检测。 在达到锁相的过程中，相位和频率检测器同时工作。 当VCO信号存在时，VCO信号与输入信号锁相。 当输入信号不存在时，VCO通过频率锁定到参考信号的倍数来维持接近预期比特率的频率。 因此，它避免了极端的系统行为，并极大地有助于在输入信号在没有时间段之后施加时的快速可靠的锁相。 PLL具有简单，低功耗和实现尽可能最佳相位分辨率的模拟功能，而频率锁定模式是数字控制的，可实现高参数不敏感，易于禁用，从而最大限度地降低一旦锁相达到时的功耗和抖动。 频率检测器包括两个用于计数VCO和参考信号的计数器。 频率检测器根据需要禁止任一计数器，迫使它们都以相同的速率进行计数，并使用禁止脉冲来控制直接连接到PLL的积分电容的独立电荷泵。 频率检测器可以轻松添加到各种电荷泵PLL中。
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公开(公告)号：EP0192411B1
公开(公告)日：1992-04-22
申请号：EP86300964.3
申请日：1986-02-12
IPC分类号： H04L25/03
CPC分类号： H04L25/03057
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公开(公告)号：EP0138346A3
公开(公告)日：1988-04-20
申请号：EP84305889
申请日：1984-08-29
CPC分类号： H04L7/033 , H03K3/0307 , H03L7/099
摘要： A variable oscillator, suitable for integration as part of a phase lock loop (PLL) clock source in a complementary metal oxide semiconductor (CMOS) integrated circuit, includes an amplifier and terminals for connection to a a tank circuit, for example a crystal resonator. A passive reactance is alternately coupled and decoupled in relation to the amplifier to cause oscillatory operation at lower and higher frequencies. In the CMOS circuit the reactance is conveniently provided by conductive layers of predetermined dimensions being carried by an oxide layer. Each layer provides a capacitive reactance which is arranged in series with a field effect defice being controlled by associated PLL control circuitry.
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