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    SONOS MEMORY DEVICE AND METHOD OF OPERATING A SONOS MEMORY DEVICE
    2.
    发明公开
    SONOS MEMORY DEVICE AND METHOD OF OPERATING A SONOS MEMORY DEVICE 审中-公开
    SONOS存储器系统及其操作方法SONOS存储安排

    公开(公告)号：EP2024978A2

    公开(公告)日：2009-02-18

    申请号：EP07735937.0

    申请日：2007-05-16

    申请人： NXP B.V.

    发明人： VAN DUUREN, Michiel, J. ,  VAN SCHAIJK, Robertus, T., F. ,  AKIL, Nader

    IPC分类号： G11C16/04 ,  G11C16/10

    CPC分类号： G11C16/0466 ,  G11C16/10

    摘要： The present invention relates to a memory device, hereinafter SONOS memory device, comprising SONOS memory cells having a control gate terminal connected to a SONOS layer stack with a nitride layer, a source terminal and a drain terminal; and a programming unit, which is connected to the drain terminal and to the control gate terminal and which is configured to apply a predetermined positive drain voltage to the drain terminal of the selected SONOS memory cell and a predetermined negative gate voltage to the control gate terminal of the selected SONOS memory cell each upon receiving a programming request addressed to a selected SONOS memory cell, the drain voltage and the gate voltage being suitable for creating hot holes at a drain side of the selected SONOS memory cell in a gate-assisted band-to-band-tunneling process and for injecting the hot holes into the nitride layer of the selected SONOS memory cell, thus switching the selected SONOS memory cell from a high-VT state to a low-VT state.

    A MEMORY CELL, A MEMORY ARRAY AND A METHOD OF PROGRAMMING A MEMORY CELL
    7.
    发明公开
    A MEMORY CELL, A MEMORY ARRAY AND A METHOD OF PROGRAMMING A MEMORY CELL 有权
    存储单元中，存储器阵列与方法编程存储器单元

    公开(公告)号：EP2137735A1

    公开(公告)日：2009-12-30

    申请号：EP08719863.6

    申请日：2008-04-01

    申请人： NXP B.V.

    发明人： AKIL, Nader ,  VAN DUUREN, Michiel

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C16/0466 ,  G11C16/0433

    摘要： A method of programming a memory cell (100), the method comprising applying a first electric potential to a first electric terminal (101) of the memory cell (100) to accelerate first charge carriers of a first type of conductivity to thereby generate second charge carriers of a second type of conductivity by impact ionisation of the accelerated first charge carriers, and applying a second electric potential to a second electric terminal (102) of the memory cell (100) to accelerate the second charge carriers to thereby inject the second charge carriers in a charge trapping structure (103) of the memory cell (100).

    NON-VOLATILE MEMORY DEVICE WITH IMPROVED DATA RETENTION
    8.
    发明公开
    NON-VOLATILE MEMORY DEVICE WITH IMPROVED DATA RETENTION 审中-公开
    具有改进的数据保留不挥发内存模块

    公开(公告)号：EP1946384A1

    公开(公告)日：2008-07-23

    申请号：EP06809563.7

    申请日：2006-10-10

    申请人： NXP B.V.

    发明人： VAN SCHAIJK, Robertus, T., F. ,  AKIL, Nader ,  SLOTBOOM, Michiel

    IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/51

    CPC分类号： H01L27/115 ,  H01L29/513 ,  H01L29/792

    摘要： A non-volatile memory device on a semiconductor substrate comprises a semiconductor base, and a programmable memory transistor comprising a storage stack, a control gate, source and drain regions and a channel in between source and drain. The storage stack comprises a first insulating layer (9) , a trapping layer (10) and a second insulating layer (11) . The first layer is positioned above the channel, the trapping layer above the first layer and the second layer above the trapping layer. Next, the control gate is arranged above the storage stack. The storage stack is arranged for trapping charge in the trapping layer by tunneling of charge carriers from the channel through the first layer which comprises a high-K material. The high-K material has a relatively smaller difference between the barrier height energy for electrons and the barrier height energy for holes in comparison to the difference between the barrier height energies for electrons and for holes in silicon dioxide .