公开(公告)号：EP3314664A1

公开(公告)日：2018-05-02

申请号：EP15896566.5

申请日：2015-06-26

Applicant: INTEL Corporation

Inventor： AVCI, Uygar E. ,  MORRIS, Daniel H. ,  YOUNG, Ian A. ,  RAMEY, Stephen M.

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/76224 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11558 ,  H01L29/0649 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/78 ,  H01L29/7851 ,  H01L29/788 ,  H01L29/7881

Abstract: Embodiments of the present disclosure provide techniques and configurations for semi-volatile embedded memory with between-fin floating gates. In one embodiment, an apparatus includes a semiconductor substrate and a floating-gate memory structure formed on the semiconductor substrate including a bitcell having first, second, and third fin structures extending from the substrate, an oxide layer disposed between the first and second fin structures and between the second and third fin structures, a gate of a first transistor disposed on the oxide layer and coupled with and extending over a top of the first fin structure, and a floating gate of a second transistor disposed on the oxide layer between the second and third fin structures. Other embodiments may be described and/or claimed.

公开(公告)号：EP3243220A1

公开(公告)日：2017-11-15

申请号：EP15819943.0

申请日：2015-12-08

Applicant: Silicon Storage Technology Inc.

Inventor： CHEN, Chun-ming ,  WU, Man-tang ,  YANG, Jeng-wei ,  SU, Chien-sheng

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: A non-volatile memory cell includes a substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type spaced apart from the first region, forming a channel region therebetween. A floating gate is disposed over and insulated from a first portion of the channel region which is adjacent the first region. A select gate is disposed over a second portion of the channel region adjacent to the second region, the select gate being formed of a metal material and being insulated from the second portion of the channel region by a layer of silicon dioxide and a layer of high K insulating material. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate.

公开(公告)号：EP2166571B1

公开(公告)日：2017-08-30

申请号：EP08764638.6

申请日：2008-05-23

Applicant: National Institute of Advanced Industrial Science and Technology

Inventor： HAYASHI, Yutaka ,  MATSUMOTO, Kazuhiko ,  KAMIMURA, Takafumi

IPC: H01L29/06 ,  H01L29/788 ,  H01L29/792 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423

CPC classification number: H01L29/7881 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28291 ,  H01L29/0657 ,  H01L29/1606 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/6684 ,  H01L29/7781 ,  H01L29/792

公开(公告)号：EP2709108B1

公开(公告)日：2017-06-21

申请号：EP13183417.8

申请日：2013-09-06

Applicant: NXP USA, Inc.

Inventor： Gasquet, Horatio P. ,  Cunningham, Jeffrey C.

IPC: H01L29/423 ,  H01L29/788 ,  G11C16/14 ,  G11C16/30 ,  G11C16/12 ,  G11C5/14

CPC classification number: G11C5/145 ,  G11C16/12 ,  G11C16/30 ,  H01L29/42332 ,  H01L29/7881

公开(公告)号：EP3120377A1

公开(公告)日：2017-01-25

申请号：EP15706621.8

申请日：2015-02-11

Applicant: Silicon Storage Technology Inc.

Inventor： SU, Chien-Sheng ,  TADAYONI, Mandana ,  TRAN, Hieu Van ,  DO, Nhan

IPC: H01L21/28 ,  H01L27/115 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L27/1203 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/1207 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7841 ,  H01L29/7881

Abstract: A semiconductor device has a silicon substrate with a first area (20) including a buried insulation layer (10b) with silicon over and under the insulation layer and a second area (22) in which the substrate lacks buried insulation disposed under any silicon. Logic MOS devices (62) are formed in the first area in the silicon (10c) that is over the insulation layer. Memory cells (49) are formed in the second area that include spaced apart second source and second drain regions (42, 48) formed in the substrate and defining a channel region (47) therebetween, a floating gate (34) disposed over and insulated from a first portion of the channel region, and a select gate (44) disposed over and insulated from a second portion of the channel region.

Abstract translation: 具有与第一区域包含与硅上和绝缘层，并且其中所述底物缺乏掩埋绝缘任何硅酮下设置的第二区域下的掩埋绝缘层的硅衬底的半导体器件。 逻辑装置在第一区域上形成具有间隔开的在有机硅形成的源区和漏区所做的是在绝缘层和导电栅极形成在和从硅酮的一部分绝缘所做的是在绝缘层和源极之间 和漏区。 存储器单元在第二区域中形成并包括间隔开的第二源极和基片形成的第二漏极区域和限定的沟道区在它们之间，浮栅设置在从所述沟道区的第一部分绝缘，且选择栅极弃置 从所述沟道区的第二部分和上绝缘。

公开(公告)号：EP3028297A1

公开(公告)日：2016-06-08

申请号：EP14756145.0

申请日：2014-07-30

Applicant: Silicon Storage Technology Inc.

Inventor： YOO, Jong-Won ,  KOTOV, Alexander ,  TKACHEV, Yuri ,  SU, Chien-Sheng

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

Abstract: A non- volatile memory cell includes a substrate of a first conductivity type with first and second spaced apart regions of a second conductivity type, forming a channel region therebetween. A select gate is insulated from and disposed over a first portion of the channel region which is adjacent to the first region. A floating gate is insulated from and disposed over a second portion of the channel region which is adjacent the second region. Metal material is formed in contact with the floating gate. A control gate is insulated from and disposed over the floating gate. An erase gate includes a first portion insulated from and disposed over the second region and is insulated from and disposed laterally adjacent to the floating gate, and a second portion insulated from and laterally adjacent to the control gate and partially extends over and vertically overlaps the floating gate.

公开(公告)号：EP2911190A4

公开(公告)日：2016-05-25

申请号：EP13847756

申请日：2013-09-27

Applicant: FLOADIA CORP

Inventor： TANIGUCHI YASUHIRO ,  KASAI HIDEO ,  SHINAGAWA YUTAKA ,  OKUYAMA KOSUKE

IPC: H01L21/8247 ,  G11C16/04 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C14/0063 ,  G11C7/18 ,  G11C8/16 ,  G11C16/04 ,  G11C16/0441 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11558 ,  H01L29/7881

公开(公告)号：EP3002778A1

公开(公告)日：2016-04-06

申请号：EP14187533.6

申请日：2014-10-02

Applicant: Elmos Semiconductor Aktiengesellschaft

Inventor： Kleining, Tobias ,  Vaitkevitch, Sergej ,  Hofmann, Martin

IPC: H01L21/28 ,  G11C16/04 ,  H01L29/423 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L21/28273 ,  G11C7/04 ,  G11C16/0425 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: Die Flash-Speicherzelle, die durch Anlegen von Programmier- und Löschspannungen beschreibbar sowie löschbar und durch Anlegen einer Lesespannung auslesbar ist, ist verstehen mit einem Halbleitersubstrat (16), in dessen Oberseite (22) voneinander beabstandete Drain- und Source-Anschlussgebiete (24,26) eingebracht sind. Ferner weist die Flash-Speicherzelle eine Gate-Isolationsschicht auf. Die Flash-Speicherzelle ist ferner mit einem Speicherelement (34) für elektrische Ladung versehen. Das Speicherelement (34) ist dezentral zwischen den Drain- und Source-Anschlussgebieten (24,26) und mit jeweiligem lateralen Abstand zu beiden positioniert. Die Flash-Speicherzelle weist eine die Gate-Isolationsschicht (30) überdeckende, das Speicherelement (34) allseitig umgebende sowie gegenüber diesem durch ein Dielektrikum (44,48) elektrisch isolierte Steuertransistor-Gate-Elektrode (32) zur Erzeugung eines wahlweise elektrisch leitenden oder sperrenden Kanals unterhalb der Steuertransistor-Gate-Elektrode (32) auf, wobei die Oberseite (22) des Halbleitersubstrats (16) unterhalb der Gate-Isolationsschicht (30) in einem Bereich zwischen dem Drain- und dem Source-Anschlussgebiet (24,26) ein laterales Dotierstoffprofil aufweist, das im Bereich unterhalb des Speicherelements (34) zur Einstellung einer relativ hohen ersten Schwellspannung einen Dotierstoff von einem ersten Leitungstyp und im Bereich unterhalb der Steuertransistor-Gate-Elektrode (32) zur Einstellung einer im Vergleich zur ersten Schwellspannung wesentlich geringeren zweiten Schwellspannung den ersten Dotierstoff (52) und einen zweiten Kompensationsdotierstoff (56) von einem zum ersten Leitungstyp entgegengesetzten zweiten Leitungstyp aufweist.

Abstract translation: 该快速存储单元，其是可写和可擦除和通过施加编程将读取电压施加读取和擦除电压，理解与半导体基板（16），在其上侧（22）间隔开的漏极和源极端子的区域（24， 26）被插入。 此外，栅极绝缘层上的快闪存储器单元。 闪速存储器单元进一步设置有用于将电荷存储元件（34）。 所述存储器元件（34）是漏极和源极末端区域（24,26）以及位于与来自两个相应的横向距离之间的分散。 闪速存储器单元包括用于产生选择性导电或栅极绝缘层（30）由电介质（44,48）电绝缘的控制晶体管栅电极（32）覆盖在所有侧面包围并相对于后者的存储器元件（34） 阻塞控制晶体管栅极电极（32），下方的通道，其中在漏极和源极端子区域之间的区域中的栅极绝缘层（30）下方的半导体基板（16）的上侧（22）（24,26） 具有横向掺杂物轮廓，其中在用于设置第一导电型的相对高的第一阈值电压和在用于设定低得多的掺杂剂控制晶体管栅电极（32）下面的范围中的存储器元件（34）下方的区域相比，所述第一阈值电压 第二阈值由电压的第一掺杂剂（52）和第二Kompensationsdotierstoff（56） 具有第二导电类型相反的第一导电类型。

公开(公告)号：EP2973717A1

公开(公告)日：2016-01-20

申请号：EP14724555.9

申请日：2014-03-13

Applicant: Microchip Technology Incorporated

Inventor： HEWITT, Kent ,  WONG, Jack ,  CHEN, Bomy ,  DARYANANI, Sonu ,  SHIELDS, Jeffrey, A. ,  ALVAREZ, Daniel ,  HYMAS, Mel

IPC: H01L29/423 ,  G11C11/56 ,  G11C16/04 ,  H01L29/66 ,  H01L29/788

CPC classification number: G11C16/0416 ,  H01L29/42328 ,  H01L29/7881

Abstract: An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate defining a write/erase path for performing high voltage write and erase operations, and a read gate defining a read path for performing low voltage read operations, wherein the read path is distinct from the write/erase path. This allows for a smaller read gate oxide, thus allowing the cell size to be reduced. Further, the EEPROM cell may include two independently controllable read gates, thereby defining two independent transistors which allows better programming voltage isolation. This allows the memory array to be drawn using a common source instead of each column of EEPROM cells needing its own source line. This makes the array more scalable because the cell x-dimension would otherwise be limited by each column needing two metal 1 pitches.

公开(公告)号：EP2948983A1

公开(公告)日：2015-12-02

申请号：EP14743125.8

申请日：2014-01-23

Applicant: Micron Technology, Inc.

Inventor： HOPKINS, John ,  FAN, Darwin Franseda ,  SIMSEK-EGE, Fatma Arzum ,  BRIGHTEN, James ,  MAURI, Aurelio Giancarlo ,  JAYANTI, Srikant

IPC: H01L27/115

CPC classification number: H01L29/7887 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7881 ,  H01L29/7889

Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.