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    TESTING OF AN INTEGRATED CIRCUIT THAT CONTAINS SECRET INFORMATION
    2.
    发明公开
    TESTING OF AN INTEGRATED CIRCUIT THAT CONTAINS SECRET INFORMATION 有权
    包含秘密信息的集成电路的测试

    公开(公告)号：EP1917535A2

    公开(公告)日：2008-05-07

    申请号：EP06795621.9

    申请日：2006-08-09

    申请人： NXP B.V.

    发明人： NIEUWLAND, Andre, K. ,  GOEL, Sandeepkumar ,  MARINISSEN, Erik, J. ,  VERMEULEN, Hubertus, G., H. ,  VRANKEN, Hendrikus, P., E.

    IPC分类号： G01R31/317

    CPC分类号： G01R31/318541 ,  G01R31/31719

    摘要： An integrated circuit (10) comprises a scan chain (14) with parallel inputs and outputs coupled to a functional circuit (12a-c). A scan chain modifying circuit (43, 47, 70a-c) is provided coupled to the scan chain (14). When testing is authorized the scan chain modifying circuit operates in a mode wherein a normal shift path is provided through the scan chain. When testing is not authorized the scan chain modifying circuit (43, 47, 70a-c) operates to effect spontaneous dynamic changes in the shift path, which dynamically vary the length of the shift path between external terminals of the integrated circuit while shifting takes place. In an embodiment the dynamical variations are controlled by a running key comparison. In other embodiments running key comparison is used to disable transfer through the scan chain and/or operation of functional circuits.

    摘要翻译： 集成电路（10）包括具有耦合到功能电路（12a-c）的并行输入和输出的扫描链（14）。 扫描链修改电路（43,47,70a-c）被提供为耦合到扫描链（14）。 当测试被授权时，扫描链修改电路以其中通过扫描链提供正常移位路径的模式操作。 当测试未被授权时，扫描链修改电路（43,47,70a-c）操作以实现移位路径中的自发动态变化，其在移位发生时动态地改变集成电路的外部端子之间的移位路径的长度 。 在一个实施例中，动态变化由运行键比较来控制。 在其他实施例中，运行密钥比较被用于禁止通过扫描链的传输和/或功能电路的操作。

    METHOD OF TESTING A MEMORY
    3.
    发明授权
    METHOD OF TESTING A MEMORY 有权
    方法内存测试

    公开(公告)号：EP1129454B1

    公开(公告)日：2009-07-08

    申请号：EP00960642.7

    申请日：2000-09-08

    申请人： NXP B.V.

    发明人： MARINISSEN, Erik, J. ,  LOUSBERG, Guillaume, E., A. ,  WIELAGE, Paul

    IPC分类号： G11C29/00 ,  G06F11/20

    CPC分类号： G11C29/44

    摘要： A memory array is tested by interfacing to a pair of a stimulus generator means for generating a sequence of row stimuli and to a response evaluator means for evaluating a sequence of responses due to the sequence of stimuli. In a non-test condition the means pair is steered in a transparent mode, in a test condition the means pair is steered in a stimulus generating mode and in a response evaluating mode, respectively, and in a subsequent repair condition row- and/or column-based repair intervention are allowed up to predetermined maximum numbers of repairable rows and columns, respectively. In particular, in the said test condition on-chip for each column tallying is done for a number of faults therein up to attaining a number of faults that exceeds the maximum number of repairable rows and then the column in question is signalled as 'must be repaired'. With respect to the signalling one or more further faults are retained that lie on a row outside a said signalled column for an associated row-based repairability. After terminating the test condition the method transfers to the repair condition through outputting the signallings and a representation of the further faults.