公开(公告)号：EP4397984A1

公开(公告)日：2024-07-10

申请号：EP23184180.0

申请日：2023-07-07

申请人： PUFsecurity Corporation

发明人： Chuang, Kai-Hsin ,  Shao, Chi-Yi ,  You, Chun-Heng

IPC分类号： G01R31/317 ,  G01R31/3167

CPC分类号： G01R31/31719 ,  G01R31/3167

摘要： An anti-tampering detector (10) and a method for detecting a physical attack are provided, wherein the anti-tampering detector (10) includes a temperature sensor (110), a voltage detector (120), a frequency detector (130) and a controller (100). The temperature sensor (110) is configured to generate a temperature code according to an operation temperature. The voltage detector (120) is configured to generate a voltage code according to a supply voltage and the temperature code. The frequency detector (130) is configured to generate a frequency code according to a system clock, the temperature code and the voltage code. The controller (100) is configured to generate an anti-tampering detection result according to the temperature code, the voltage code and the frequency code. The anti-tampering detection result indicates whether any of the operation temperature, the supply voltage and the system clock is tampered with due to the physical attack.

公开(公告)号：EP3220305B1

公开(公告)日：2018-10-31

申请号：EP17156290.3

申请日：2017-02-15

申请人： ESHARD

发明人： THIEBEAULD DE LA CROUEE, Hugues ,  WURCKER, Antoine

IPC分类号： G06F21/72 ,  G06F21/75 ,  G09C1/00 ,  G01R31/317 ,  H04L9/00

CPC分类号： H04L9/003 ,  G01R31/31719 ,  G06F21/72 ,  G06F21/75 ,  G09C1/00 ,  H04L9/002 ,  H04L9/3242 ,  H04L9/3247 ,  H04L9/3249 ,  H04L9/3252 ,  H04L2209/08 ,  H04L2209/12

摘要： The present invention relates to a test method of a circuit, comprising: acquiring a plurality of value sets comprising values of a physical quantity linked to the activity of a circuit to be tested when the circuit executes an operation of a set of distinct cryptographic operations applied to a secret data, selecting at least a first subset in each value set, for each value set, counting by a processing unit occurrence numbers of values transformed by a first surjective function applied to the values of the first subset of the value set, to form an occurrence number set for the value set, for each operation of the operation set, and each of the possible values of a part of the secret data, computing a partial operation result, computing cumulative occurrence number sets (CH) by adding the occurrence number sets corresponding to the operations of the operation set, which when applied to a same value or equivalent value of the possible values of the part of the secret data, provide a partial operation result having a same transformed value resulting from the application of a second surjective function, merging according to a selected merging scheme, cumulative occurrence numbers in the cumulative occurrence number sets (HT), and analyzing the merged cumulative occurrence number sets (HTR1) to determine the part of the secret data.

公开(公告)号：EP3220305A1

公开(公告)日：2017-09-20

申请号：EP17156290.3

申请日：2017-02-15

申请人： ESHARD

发明人： THIEBEAULD DE LA CROUEE, Hugues ,  WURCKER, Antoine

IPC分类号： G06F21/55 ,  H04L9/00 ,  G01R31/317

CPC分类号： H04L9/003 ,  G01R31/31719 ,  G06F21/72 ,  G06F21/75 ,  G09C1/00 ,  H04L9/002 ,  H04L9/3242 ,  H04L9/3247 ,  H04L9/3249 ,  H04L9/3252 ,  H04L2209/08 ,  H04L2209/12

摘要： The present invention relates to a test method comprising: acquiring a plurality of value sets (Ci), each value set comprising measurements or logic signals, linked to the activity of a circuit to be tested when it executes an operation of a set of distinct cryptographic operations applied to a same secret data, selecting at least two subsets (EC1 i, EC2i) of values in each value set (Ci), for each value set, computing combined values (Wi) combining together one value in each value subset, for each value set, counting occurrence numbers of values transformed by a first surjective function applied to the combined values of the value set, for each operation of the operation set, and each possible values of a part of the secret data, computing a partial operation result, computing cumulative occurrence number sets obtained by adding the occurrence number sets corresponding to the operations of the operation set, which when applied to a same value of the possible values of the part of the secret data, provide a partial operation result having a same transformed value by a second surjective function, and analyzing the cumulative occurrence number sets to determine the part of the secret data.

摘要翻译： 本发明涉及一种测试方法，包括：当其执行一组不同的密码术的操作时，获取与待测试电路的活动相关联的多个值集（Ci），每个值集包括测量或逻辑信号 应用于相同秘密数据的操作，针对每个值集合选择每个值集合（Ci）中的值的至少两个子集（EC1 i，EC2i），计算将每个值子集中的一个值组合为一起的组合值（Wi） 每个值集合，针对操作集合的每个操作对由应用于值集合的组合值的第一全射函数所变换的值的出现次数和部分秘密​​数据的每个可能值进行计数，计算部分操作结果 ，计算通过将与操作集的操作相对应的出现次数集相加而获得的累积出现次数集，所述出现次数集在应用于所述操作集的所述部分的可能值的相同值时 秘密数据，通过第二全息函数提供具有相同变换值的部分运算结果，并分析累计出现次数集合以确定部分秘密数据。

公开(公告)号：EP3073412A1

公开(公告)日：2016-09-28

申请号：EP16161724.6

申请日：2016-03-22

申请人： Freescale Semiconductor, Inc.

发明人： ARORA, Mohit ,  MCQUIRK, Dale ,  BHARGAVA, Prashant ,  GALLIMORE, Simon ,  SEABERG, Charles

IPC分类号： G06F21/86

CPC分类号： G06F21/86 ,  G01K3/005 ,  G01R31/31719 ,  G06F21/71 ,  G06F21/755 ,  G06F21/81

摘要： A processing system includes a processor and a temperature security module coupled to provide a temperature tamper signal to the processor. The temperature security module includes a shelf mode trim value, an operating mode trim value, and a programmable temperature trim value. One of the programmable temperature trim value, the shelf mode trim value, and the operating mode trim value, is used based on a deployment mode of the processing system to set a temperature monitor trim value.

摘要翻译： 处理系统包括处理器和温度安全模块，其被耦合以向处理器提供温度篡改信号。 温度安全模块包括搁板模式修整值，操作模式修整值和可编程温度修剪值。 基于处理系统的部署模式来设置温度监视器修整值，可以使用可编程温度修正值，搁架模式修整值和操作模式修整值之一。

公开(公告)号：EP2983103A1

公开(公告)日：2016-02-10

申请号：EP15177804.0

申请日：2015-07-22

申请人： EM Microelectronic-Marin SA

发明人： Walter, Fabrice

IPC分类号： G06F21/55 ,  G06F21/75

CPC分类号： G01R31/31727 ,  G01R31/31719 ,  G06F21/554 ,  G06F21/75 ,  H03K19/003

摘要： A circuit configuration for secure application includes several internal frequency detectors (10) arranged in digital units at critical points of an integrated circuit (30). The clock detectors (10) are concealed in the digital part of the integrated circuit (30) each as a standard cell (flip-flop unit) in order to prevent any external manipulation and in order to hide its function. The clock detectors (10) are preferably disposed in a clock tree topology, which can be at several levels for distributing the clock signal through the different digital unit tree at critical points. Alarms are generated via a clock detector network if at any level an external clock attack has been monitored.

摘要翻译： 用于安全应用的电路配置包括在集成电路（30）的关键点处以数字单元布置的多个内部频率检测器（10）。 时钟检测器（10）隐藏在集成电路（30）的数字部分中，每个都作为标准单元（触发器单元），以防止任何外部操作并且隐藏其功能。 时钟检测器（10）优选地布置在时钟树拓扑中，该时钟树拓扑可以处于几个级别，用于在关键点处通过不同的数字单元树来分配时钟信号。 如果在任何级别监测到外部时钟攻击，则通过时钟检测器网络生成警报。

公开(公告)号：EP2574944B1

公开(公告)日：2014-11-05

申请号：EP12180652.5

申请日：2012-08-16

申请人： Oberthur Technologies

发明人： Morin, Nicolas ,  Giraud, Christophe

IPC分类号： G01R31/317

CPC分类号： G01R31/31719

公开(公告)号：EP2583112A1

公开(公告)日：2013-04-24

申请号：EP11728119.6

申请日：2011-06-13

申请人： Alcatel Lucent

发明人： GOYAL, Suresh ,  PORTOLAN, Michele ,  VAN TREUREN, Bradford

IPC分类号： G01R31/3185 ,  G01R31/317

CPC分类号： G01R31/31719 ,  G01R31/318572

摘要： A scan chain security capability is provided herein. The scan chain security capability enables secure control over normal use of a scan chain of a system, e.g., for purposes such as testing prior to deployment or sale of the system, in-field testing after deployment or sale of the system, in-field modification of the system, and the like. The scan chain security capability enables secure control over normal use of a scan chain by enabling control over interruption of a scan chain and re-establishment of an interrupted scan chain. A scan chain security component is configured for removing an open-circuit condition from the scan chain in response to a control signal. The control signal may be generated in response to validation of a security key, in response to successful completion of a challenge-based authentication process, or in response to any other suitable validation or authentication. The scan chain security component also may be configured for creating an open-circuit condition in the scan chain in response to a second control signal. The second control signal may be a scan register value received via the scan chain.

公开(公告)号：EP2282280A1

公开(公告)日：2011-02-09

申请号：EP10011274.7

申请日：2005-03-30

申请人： Emma Mixed Signal C.V.

发明人： Griesdorf, Dustin ,  Rooks, Alan ,  Nielsen, Jakob ,  Schneider, Todd

IPC分类号： G06F21/00 ,  H04R25/00

CPC分类号： G06F21/79 ,  G01R31/31719 ,  G06F12/1433 ,  G06F21/74 ,  G06F2221/2105 ,  G06F2221/2143 ,  H04R25/556 ,  H04R25/70 ,  H04R2225/61

摘要： Method and system for protecting content in a programmable system is provided. The system is connectable to an external device through one or more access ports. Content protection method/manager is implemented by assigning one or more access modes to the access port and switching the access modes. In response to a current access mode, the content protection method/manager restricts visibility of the system to the external device via the access port.

摘要翻译： 提供了一种用于保护可编程系统中的内容的方法和系统。 该系统可通过一个或多个访问端口连接到外部设备。 通过向访问端口分配一个或多个访问模式并切换访问模式来实现内容保护方法/管理器。 响应于当前访问模式，内容保护方法/管理器通过访问端口将系统的可视性限制到外部设备。

公开(公告)号：EP1455259B1

公开(公告)日：2010-12-01

申请号：EP04300094.2

申请日：2004-02-23

申请人： STMicroelectronics S.A.

发明人： Zahra, Claude ,  Teglia, Yannick

IPC分类号： G06F21/02

CPC分类号： G06F21/74 ,  G01R31/31719

公开(公告)号：EP2248061A1

公开(公告)日：2010-11-10

申请号：EP09715962.8

申请日：2009-02-11

申请人： Institut Telecom - Telecom Paris Tech

发明人： GUILLEY, Sylvain ,  DANGER, Jean-Luc

IPC分类号： G06F21/00 ,  G01R31/317

CPC分类号： G01R31/31719 ,  G06F21/75 ,  G06F21/755 ,  H04L9/003 ,  H04L9/0625 ,  H04L2209/125 ,  H04L2209/127 ,  H04L2209/26

摘要： The invention relates to a method for testing cryptographic circuits. The invention also relates to a cryptographic circuit that can be tested, the cryptographic circuit including registers and logic gates (211, 212, 213, 214). According to the invention, a test comprises carrying out a differential consumption analysis (DPA) of the circuit registers. In a cryptographic circuit being secured and including a first half-circuit (211, 214) combined with a second half-circuit (212, 213) operating in a complementary logic, the power supply (Vdd1, 23, 25) of the first half-circuit is separated from the power supply (Vdd2, 24) of the second half-circuit, the differential consumption analysis being carried out in parallel on each half-circuit and both power supplies being grouped together into the same power supply after the test.