公开(公告)号：EP3240142A1

公开(公告)日：2017-11-01

申请号：EP17163997.4

申请日：2017-03-30

申请人： NXP B.V.

发明人： Crosby, Robert, Glenn ll ,  Christiaans, Peter ,  Wu, Qiong

IPC分类号： H02J50/12

摘要： A wireless charging receiver operates on a resonance principle and includes an impedance matching circuit coupled between an antenna and a rectifier circuit. The impedance matching circuit has both series-connected and parallel-connected capacitors. At least one of the capacitors is a tunable variable capacitor. A method is provided for automatically adjusting a capacitance value of the at least one variable capacitor based on an error voltage between a target rectifier voltage and a measured rectifier voltage. Automatically adjusting the antenna impedance of the receiver provides for improved power transfer efficiency for changing operating conditions. In one embodiment, one or more of the parallel-connected capacitors are variable capacitors. In another embodiment, one or more of the series-connected capacitors are variable capacitors.

摘要翻译： 无线充电接收器根据谐振原理工作并且包括耦合在天线和整流器电路之间的阻抗匹配电路。 阻抗匹配电路具有串联和并联电容器。 至少有一个电容是可调电容。 提供了一种用于基于目标整流器电压和测量的整流器电压之间的误差电压自动调整至少一个可变电容器的电容值的方法。 自动调整接收器的天线阻抗可改善电源传输效率，以改变工作条件。 在一个实施例中，一个或多个并联连接的电容器是可变电容器。 在另一个实施例中，串联连接的电容器中的一个或多个是可变电容器。

公开(公告)号：EP2330741A2

公开(公告)日：2011-06-08

申请号：EP10193417.2

申请日：2010-12-02

申请人： NXP B.V.

发明人： Wu, Qiong ,  Mahooti, Kevin

IPC分类号： H03K17/16

CPC分类号： H03K17/063 ,  G11C27/02 ,  G11C27/024 ,  H03K17/145 ,  H03K17/162 ,  H03K2217/0018

摘要： An analog sample-and-hold switch has parallel branches extending from an input node to an output node connected to a hold capacitor, each branch having a PMOS signal switch FET in series with a PMOS dummy FET. A sample clock controls on-off switching of the PMOS signal switch FETs, and an inverse of the sample clock controls a complementary on-off switching of the PMOS dummy FETs. A bias sequencer circuit biases the PMOS signal switch FETs and biases the PMOS dummy FETs, in a complementary manner, synchronous with their respective on-off states. The on-off switching of the PMOS dummy FETs injects charge cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs.

摘要翻译： 模拟采样保持开关具有从输入节点延伸到连接到保持电容器的输出节点的并行分支，每个分支具有与PMOS伪FET串联的PMOS信号开关FET。 采样时钟控制PMOS信号开关FET的导通截止切换，并且采样时钟的反相控制PMOS虚拟FET的互补开 - 关切换。 偏置顺序器电路以PMOS互补方式偏置PMOS信号开关FET并且以与它们各自的开关状态同步的方式偏置PMOS虚拟FET。 PMOS虚拟FET的开 - 关切换由PMOS信号开关FET注入电荷消除电荷注入，并且注入消除由PMOS信号开关FET注入的毛刺的毛刺。

公开(公告)号：EP2579464A3

公开(公告)日：2016-11-16

申请号：EP12185619.9

申请日：2012-09-24

申请人： NXP B.V.

发明人： Wu, Qiong ,  Mahooti, Kevin

IPC分类号： H03M1/10 ,  H03M1/46

CPC分类号： H03M1/1047 ,  H03M1/1052 ,  H03M1/462 ,  H03M1/468

摘要： A method and apparatus for correcting the offset and linearity error of a data acquisition system. A charge redistribution digital to analog convertor (CDAC) is connected to one of the differential inputs of a comparator whose second input comes from a function CDAC. The calibration algorithm is built into a digital control unit. The digital control unit detects the offset and capacitor mismatch errors sequentially, stores the calibration codes for each error in calibration mode and provides the input-dependent error correction signals synchronized with the binary search timing to adjust the differential input of the comparator and compensate the input-dependent errors present at the output of the non-ideal function CDAC during normal conversions.

公开(公告)号：EP2579464A2

公开(公告)日：2013-04-10

申请号：EP12185619.9

申请日：2012-09-24

申请人： NXP B.V.

发明人： Wu, Qiong ,  Mahooti, Kevin

IPC分类号： H03M1/10 ,  H03M1/46

CPC分类号： H03M1/1047 ,  H03M1/1052 ,  H03M1/462 ,  H03M1/468

摘要： A method and apparatus for correcting the offset and linearity error of a data acquisition system. A charge redistribution digital to analog convertor (CDAC) is connected to one of the differential inputs of a comparator whose second input comes from a function CDAC. The calibration algorithm is built into a digital control unit. The digital control unit detects the offset and capacitor mismatch errors sequentially, stores the calibration codes for each error in calibration mode and provides the input-dependent error correction signals synchronized with the binary search timing to adjust the differential input of the comparator and compensate the input-dependent errors present at the output of the non-ideal function CDAC during normal conversions.

摘要翻译： 一种用于校正数据采集系统的偏移和线性误差的方法和装置。电荷再分配数字 - 模拟转换器（CDAC）被连接到的比较器，其第二输入来自功能CDAC的差分输入端之一。 校准算法被内置到的数字控制单元。 数字控制单元检测的偏移量和电容器失配误差随后，存储校准代码用于在校准模式下每个错误并提供与二进制搜索定时同步以调整比较器的差分输入和补偿输入的输入有关的误差校正信号 依赖性误差存在于非理想功能CDAC的在正常转换的输出。

公开(公告)号：EP3240142B1

公开(公告)日：2020-05-06

申请号：EP17163997.4

申请日：2017-03-30

申请人： NXP B.V.

发明人： Crosby, Robert, Glenn ll ,  Christiaans, Peter ,  Wu, Qiong

IPC分类号： H02J50/12

公开(公告)号：EP2330741A3

公开(公告)日：2014-09-17

申请号：EP10193417.2

申请日：2010-12-02

申请人： NXP B.V.

发明人： Wu, Qiong ,  Mahooti, Kevin

IPC分类号： H03K17/16 ,  G11C27/02 ,  H03K17/06 ,  H03K17/14

CPC分类号： H03K17/063 ,  G11C27/02 ,  G11C27/024 ,  H03K17/145 ,  H03K17/162 ,  H03K2217/0018

摘要： An analog sample-and-hold switch has parallel branches extending from an input node to an output node connected to a hold capacitor, each branch having a PMOS signal switch FET in series with a PMOS dummy FET. A sample clock controls on-off switching of the PMOS signal switch FETs, and an inverse of the sample clock controls a complementary on-off switching of the PMOS dummy FETs. A bias sequencer circuit biases the PMOS signal switch FETs and biases the PMOS dummy FETs, in a complementary manner, synchronous with their respective on-off states. The on-off switching of the PMOS dummy FETs injects charge cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs.

公开(公告)号：EP2341622A3

公开(公告)日：2014-09-24

申请号：EP10193420.6

申请日：2010-12-02

申请人： NXP B.V.

发明人： Wu, Qiong ,  Mahooti, Kevin

IPC分类号： H03K17/16 ,  H03K17/0412 ,  G11C27/02

CPC分类号： H03K17/162 ,  G11C27/02 ,  G11C27/024 ,  H03K17/04123

摘要： A sample-and-hold feed switch has parallel PMOS branches and parallel NMOS branches, each extending from an input node to an output node connected to a hold capacitor. Each PMOS branch has a PMOS switch FET connected to a matching PMOS dummy FET, and each NMOS branch has an NMOS switch FET connected to a matching NMOS dummy FET. A sample clock switches the PMOS switch FETs on and off, and a synchronous inverse sample clock effects complementary on-off switching of the PMOS dummy FETs. Concurrently, a synchronous inverse sample clock switches the NMOS switch FETs on and off, and the sample clock effects a complementary on-off switching of the NMOS dummy FETs. A bias sequencer circuit biases the bodies of the PMOS switch FETs and the bodies of the PMOS dummy FETs, in a complementary manner, and biases the NMOS switch FETs and the NMOS dummy FETs, also in a complementary manner. The on-off switching of the PMOS dummy FETs injects charge, cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs. The on-off switching of the NMOS dummy FETs injects charge that cancels a charge injection by the NMOS signal switch FETs, and injects glitches that cancels glitches injected by the NMOS signal switch FETs.

公开(公告)号：EP2341622A2

公开(公告)日：2011-07-06

申请号：EP10193420.6

申请日：2010-12-02

申请人： NXP B.V.

发明人： Wu, Qiong ,  Mahooti, Kevin

IPC分类号： H03K17/16

CPC分类号： H03K17/162 ,  G11C27/02 ,  G11C27/024 ,  H03K17/04123

摘要： A sample-and-hold feed switch has parallel PMOS branches and parallel NMOS branches, each extending from an input node to an output node connected to a hold capacitor. Each PMOS branch has a PMOS switch FET connected to a matching PMOS dummy FET, and each NMOS branch has an NMOS switch FET connected to a matching NMOS dummy FET. A sample clock switches the PMOS switch FETs on and off, and a synchronous inverse sample clock effects complementary on-off switching of the PMOS dummy FETs. Concurrently, a synchronous inverse sample clock switches the NMOS switch FETs on and off, and the sample clock effects a complementary on-off switching of the NMOS dummy FETs. A bias sequencer circuit biases the bodies of the PMOS switch FETs and the bodies of the PMOS dummy FETs, in a complementary manner, and biases the NMOS switch FETs and the NMOS dummy FETs, also in a complementary manner. The on-off switching of the PMOS dummy FETs injects charge, cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs. The on-off switching of the NMOS dummy FETs injects charge that cancels a charge injection by the NMOS signal switch FETs, and injects glitches that cancels glitches injected by the NMOS signal switch FETs.

摘要翻译： 采样保持馈电开关具有并联的PMOS分支和并联的NMOS分支，每个分支从输入节点延伸到连接到保持电容器的输出节点。 每个PMOS分支具有连接到匹配的PMOS虚拟FET的PMOS开关FET，并且每个NMOS分支具有连接到匹配的NMOS虚拟FET的NMOS开关FET。 采样时钟打开和关闭PMOS开关FET，同步反相采样时钟产生PMOS伪FET的互补开关开关。 同时，同步反相采样时钟关断NMOS开关FET，采样时钟实现NMOS虚拟FET的互补开 - 关切换。 偏置顺控器电路以互补的方式偏置PMOS开关FET的主体和PMOS虚设FET的主体，并且也以互补的方式偏置NMOS开关FET和NMOS虚拟FET。 PMOS虚拟FET的开 - 关切换注入电荷，消除PMOS信号开关FET的电荷注入，并且注入由PMOS信号开关FET注入的毛刺消除毛刺。 NMOS虚拟FET的开 - 关切换注入由NMOS信号开关FET取消电荷注入的电荷，并且注入消除由NMOS信号开关FET注入的毛刺的毛刺。