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    A GATE DRIVER CIRCUIT
    5.
    发明公开
    A GATE DRIVER CIRCUIT 审中-公开

    公开(公告)号：EP4376300A1

    公开(公告)日：2024-05-29

    申请号：EP22208812.2

    申请日：2022-11-22

    申请人： NXP USA, Inc.

    发明人： KANDAH, Ibrahim Shihadeh ,  RUDIAK, Jerry ,  EVERSON, Steven Ray

    IPC分类号： H03K17/12 ,  H03K17/16

    CPC分类号： H03K17/162 ,  H03K17/12

    摘要： A gate driver circuit for driving the gate of a power device. The gate driver circuit comprises: a gate monitoring terminal, which is connectable to the gate of the power device such that a gate voltage signal is receivable at the gate monitoring terminal; a first comparator configured to compare the gate voltage signal with a first threshold value to provide a first gate monitor signal; a second comparator configured to compare the gate voltage signal with a second threshold value, which is different to the first threshold value, to provide a second gate monitor signal; and a controller. The controller is configured to: determine a gate slew rate based on the period of time between the first gate monitor signal and the second gate monitor signal changing value for a transition in the gate voltage signal; compare the gate slew rate with a slew rate threshold; and provide an output signal based on the result of the comparison between the gate slew rate with the slew rate threshold.

    CIRCUIT FOR CONTROLLING THE SLEW RATE OF A TRANSISTOR
    6.
    发明公开
    CIRCUIT FOR CONTROLLING THE SLEW RATE OF A TRANSISTOR 审中-实审

    公开(公告)号：EP4354733A3

    公开(公告)日：2024-05-29

    申请号：EP23196216.8

    申请日：2023-09-08

    申请人： GlobalFoundries U.S. Inc.

    发明人： Sharma, Santosh

    IPC分类号： H03K17/16 ,  H03K17/687

    CPC分类号： H03K17/162 ,  H03K17/165 ,  H03K17/163 ,  H03K17/168 ,  H03K17/6871 ,  H03K2017/687520130101

    摘要： Disclosed are circuits for controlling slew rate of a transistor during switching. Each circuit includes a first transistor (e.g., a gallium nitride (GaN)-based high electron mobility transistor (HEMT) or metal-insulator-semiconductor HEMT (MISHEMT)), a capacitor, and a second transistor. The first transistor includes a first gate connected to a pad for receiving a pulse-width modulation (PWM) signal, a first drain region connected to a first plate of the capacitor, and a first source region. The second transistor includes a second gate connected to a second plate of the capacitor, a second drain region, and a second source region and is connected to both the pad and the first transistor. The connection between the first and second transistors varies depending on whether the first transistor is an enhancement or depletion mode device and on whether the slew rate control is employed for on state or off state switching.